There are some limitations in the application of electrical muscle stimulation (EMS) in virtual reality (VR) that provides precise force feedback to the fingers. To address this issue, we propose EMS-Grasping, an interaction technique that combines biomechanical simulation model with EMS. This work makes two key contributions: (1) an EMS-based musculoskeletal model of the hand is constructed to establish the relationship between the electrical stimulation intensity and the angle of the finger joint; (2) a simulation model-based method for EMS control of finger fixation at a target angle is proposed and applied to grasping virtual objects in VR. In the first experiment, we verified the reliability of the simulation model. In the second experiment, we compared three interaction models to evaluate the performance of EMS-Grasping. The results show that EMS-Grasping not only effectively reduces finger penetration with virtual objects, but also enhances the user experience in terms of realism and comfort. This implies that EMS-Grasping has good potential in expressing grasping virtual objects.

With the development of the Internet of Things (IoT), in-sensor computing techniques, such as the frame differencing and edge detection, is an effective solution for reducing large-scale sensing data transmission activities and related costs by eliminating the spatiotemporal redundancy. In these in-sensor computing tasks, thin-film transistor (TFT) technologies have gained particular interest because of their inherent support for large-area sensing-computing integration. However, existing TFT-based in-sensor computing works face challenges of high device variations, high-cost analog readouts and insufficient optimization of sequential redundancy. To address these challenges, we propose a robust spatiotemporal optimization-based in-sensor computing architecture, enabling low-power, low-latency, and efficient data compression. By combining frame differencing and edge detection, the data sparsity is greatly improved while the data movement is reduced. We develop a 4μm low-temperature polysilicon (LTPS) TFT digital standard cell library and implement a Rice compression encoder based on it. The system-level evaluations exhibit 21.5× compression ratio, 6.9× energy efficiency and 5.2× speedup improvement compared with traditional compression schemes in large-area scenarios.

In-sensor computing has emerged as a promising approach to mitigating huge data transmission costs between sensors and processing units. Recently, the emerging application scenarios have raised more demands of sensory technology for large-area and flexible integration. However, with thin-film technologies that are capable of providing flexible and large-area integration support, the implementation of in-sensor computing can be strongly restricted due to the low device performance, large-area integration variation, and costly interface between sensors and CMOS processors. To address this challenge, we propose an in-sensor computing architecture to facilitate high-parallelism NN pre-processing and effective data compression. The boundaries of computing parallelism are expanded by adopting compact ROM-based compute-in-memory scheme next to sensing array. Differential-frame computing provides not only excellent robustness, but also high data sparsity. A bio-inspired data compression method with residual recovery caches and zero-skip circuits further enhances output sparsity without accumulated error. Based on the proposed cross-layer design optimization, an LTPS TFT-based ROM CiM chip has been fabricated and experimentally measured. The system-level evaluation demonstrates 3.85× speedup and 5.10× energy efficiency improvement compared with traditional architecture with separated sensors and processors, outperforming existing in-sensor computing works in large-area thin-film technology scenarios.

In the era of intelligent IoT, huge amount of sensor data is collected and then transmitted to processor elements in edge devices or cloud servers. The latency and energy consumption in this process have been a bottleneck and are becoming more severe. To mitigate this problem, the idea of combining sensors, memory and processors for collectively handling the data, has been proposed and explored actively in recent efforts. In this work, thin-film transistor (TFT), which has been widely adopted in display devices and flexible sensors, is exploited. It is shown that, while TFT is promising for large-area sensing, it also shows a great potential for computing and storing data for large-area and low-cost edge sensors. More specifically, we have fabricated and measured two large-area TFT-based near-sensor computing-in-memory (CiM) chips adopting embedded DRAM (eDRAM) and ROM structure respectively. We further give a detailed analysis of the integration of CiM arrays and sensor arrays to realize a sensing and data pre-process system. Measurement and simulation results show that such TFT-based solutions can accomplish real-time sensing and multiply-accumulate (MAC) processing in the analog field, which simplifies the system design with lowered energy and latency in our neural network evaluations.

Anomaly detection is an important task that improves the maturity and stability of a software during its development. System logs record rich information about the running states of the software and reveal key insights of anomalous behaviors. This paper addresses anomaly detection using system log data and aims to resolve two challenges: First, different from most existing supervised learning-based anomaly detection methods that rely heavily on expensive, manually-curated labels, we aim to design an algorithm to make the most of scarce label information. Second, as a typical software system would contain very few anomalies, we aim to address the data imbalance issue which is often overlooked by existing studies. To address the challenges above, we propose LGLog, a semi-supervised anomaly detection framework that is based on system logs. First, LGLog transforms log sequences into graphs and employs an unsupervised graph learning model for pre-training. Then, LGLog mitigates the data imbalance issue by learning significant latent space representation of log events via reconstruction loss and node invariance loss, and further applies a weight balance method. Experiments indicate that LGLog outperforms compared approaches, and demonstrates the effectiveness of LGLog in the presence of scarce labels and imbalanced log data.

The rapid development of edge artificial intelligence (AI) raises high requirements for data-intensive neural network (NN) computing and storage of edge devices, under a limited chip footprint and energy supply source. As a promising approach for energy-efficient processing, computing-in-memory (CiM) has been widely explored in recent efforts to mitigate the data transmission bottleneck. However, CiM with small on-chip memory capacity results in expensive data reloads, limiting its deployment in large-scale NN applications. Moreover, the increased leakage under advanced CMOS scaling lowers the energy efficiency. In this work, device-circuit synergy based on the indium-gallium-zinc-oxide (IGZO) thin-film transistor (TFT) is adopted to address these challenges. First, 4-transistor-1-capacitor (4T1C) IGZO eDRAM CiM is proposed with higher density than SRAM-based CiM and enhanced data retention by both lower device leakage and a differential cell structure. Second, exploiting the back-end-of-line (BEOL) compatibility and vertical integration of emerging channel-all-around (CAA) IGZO devices, 3D eDRAM CiM is proposed, which paves the way for IGZO-based CiM with ultra-high density. Circuit techniques including time-interleaved computing and differential refresh are proposed to guarantee accuracy under large-capacity 3D CiM. As a proof of concept, a$128 \times 32$CiM array is fabricated under a foundry low-temperature poly-crystalline and oxide (LTPO) technology, demonstrating high computing linearity and long data retention. Benchmarks on scaled 45nm IGZO technology show energy efficiency of 686 TOPS/W for array only, and 138 TOPS/W while considering peripheral overheads.

In the era of Intelligent IoT, huge amount of sensor data is collected and then transmitted to processor elements in edge devices or cloud servers. The latency and energy consumption in this process have been a bottleneck and are becoming more severe. To mitigate this problem, the idea of combining sensors, memory and processors for collectively handling the data, has been proposed and explored actively in recent efforts. In this work, thin-film transistor (TFT), which has been widely adopted in display devices and flexible sensors, is exploited. It is shown that, while TFT is promising for near-sensor processing architecture, it also shows a great potential for computing and storage for large-area and low-cost edge sensors. More specifically, we propose an almost-nonvolatile near-sensor computing-in-memory (CiM) array based on indium-gallium- zinc-oxide (IGZO) TFT, and further, integrate the CiM array with a sensor array to be a sensing and data pre-process system. We show that such a TFT-based solution can accomplish realtime sensing and multiply-and-accumulate (MAC) processing in the analog field, which simplifies the system design with lowered energy and latency in our neural network evaluations.

With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 1990s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interest in incorporating ML to solve EDA tasks. In this article, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

Memristor-based logic design gives an alternative solution to improve the energy efficiency of computing systems, benefiting from combining the memory with computing units. Inspired by this thought, previous work has demonstrated various memristor-based logic families with different attributes and computation patterns. Besides, some logic synthesis tools are designed for specific memristive logic implementations. However, the poor universality and the neglect of realistic constraints in memory largely restrict the utility of these logic synthesis tools. In this paper, we propose a general logic synthesis framework for memristor-based logic design, containing a universal abstract description method for memristive logic, a mapping rules generator, and a synthesis and mapping flow. The proposed logic synthesis framework is suitable for various types of existing memristor-based logic families and takes the memory status into consideration. It is also possible to handle future memristive devices and logic families by providing the universal abstraction interface. Furthermore, we also design a circuit-partitioning-based synthesis acceleration strategy to tackle with the long synthesis time problem. Experimental results show that, our framework can generate mapping results under the restriction of limited resource, while the existing synthesis tools may fail under the same restriction, and achieve comparable synthesis results with the same resource as the existing synthesis tools, which is enough for computation and storage. And the proposed acceleration scheme can achieve ~ 1000× speedup compared with the initial one.