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Mireya Paredes

dblp:179/2116 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2020
0000-0002-7149-4592ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 56% High-performance computing · 28% Processor architecture and microarchitecture · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel algorithms › graph algorithms
breadth-first search
0.412020
Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi · IEEE Trans. Parallel Distributed Syst. 2020
Parallel and multicore computing
graph processing
0.412020
Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi · IEEE Trans. Parallel Distributed Syst. 2020
High-performance computing › code optimization
vectorization
0.412020
Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi · IEEE Trans. Parallel Distributed Syst. 2020
Processor architecture and microarchitecture › many-core architecture
intel xeon phi
0.112020
Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi · IEEE Trans. Parallel Distributed Syst. 2020
Processor architecture and microarchitecture
many-core architecture
0.112020
Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi · IEEE Trans. Parallel Distributed Syst. 2020

Methods — techniques the papers use, named apart from their topics

vectorization · 0.4hybrid top-down/bottom-up BFS · 0.4
YearPublicationVenuePosition
2020 Exploiting Parallelism and Vectorisation in Breadth-First Search for the Intel Xeon Phi
abstract
Modern applications generate massive amounts of data that is challenging to process or analyse. Graph algorithms have emerged as a solution for the analysis of such data because they can represent the entities participating in the generation of large-scale datasets in terms of vertices and their relationships in terms of edges. Graph analysis algorithms are used for finding patterns within these relationships, aiming to extract information to be further analysed. The breadth-first search (BFS) is one of the main graph search algorithms used for graph analysis and its optimisation has been widely researched using different parallel computers. However, the parallelisation of BFS has been shown to be challenging because of its inherent characteristics, including irregular memory access patterns, data dependencies and workload imbalance, that limit its scalability. This paper investigates the optimisation of the BFS on the Xeon Phi (Knights Corner), a modern parallel architecture provided with an advanced vector processor supporting the AVX-512 instruction set, using a bespoke development framework integrated with the Graph 500 benchmark. In addition, to demonstrate portability, we show results for a direct port of the algorithms to a more recent version of the Xeon Phi (Knights Landing) and to a Skylake CPU which supports most of the AVX-512 instruction set. Optimised parallel versions of two high-level algorithms for BFS were created using vectorisation, starting with the conventional top-down BFS algorithm and, building on this, a hybrid BFS algorithm. On the KNC our best implementations result in speedups of 1.37x (top-down) and 1.37x (hybrid), for a one million vertices graph, compared to the state-of-the-art. On the KNL and Skylake, the performance is higher than on KNC. In addition, we show results of our best hybrid algorithm on real-world graphs from the SNAP datasets with speedups up to 1.3x on KNC. Performance on KNL and Skylake is again higher, demonstrating the robustness and portability of our algorithm. The hybrid BFS algorithm can be further used to speed up other graph analysis algorithms and the lessons learned from vectorisation can be applied to other algorithms targeting existing and future models of the Xeon Phi and other advanced vector architectures.
Mireya Paredes, Graham D. Riley, Mikel Luján
IEEE Trans. Parallel Distributed Syst.1