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Arash Pourhabibi Zarandi

dblp:179/2944 · DBLP profile ↗
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4ranked-venue papers
2as first author
2since 2021 · last 2021
0000-0002-9214-5981ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Hardware accelerators and domain-specific architectures · 57% Cloud and datacenter computing · 28% Distributed systems · 15%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%
Computer networks
1 paper
Internet architecture and protocols · 50% Datacenter networks · 50%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cloud and datacenter computing
microservices
0.922021
Cerebros: Evading the RPC Tax in Datacenters · MICRO 2021
Optimus Prime: Accelerating Data Transformation in Servers · ASPLOS 2020
Machine learning › Efficient and distributed learning
distributed training
0.512021
Equinox: Training (for Free) on a Custom Inference Accelerator · MICRO 2021
Hardware accelerators and domain-specific architectures › machine learning accelerator
inference accelerator
0.512021
Equinox: Training (for Free) on a Custom Inference Accelerator · MICRO 2021
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.512021
Equinox: Training (for Free) on a Custom Inference Accelerator · MICRO 2021
Hardware accelerators and domain-specific architectures › network accelerator
network interface accelerator
0.512021
Cerebros: Evading the RPC Tax in Datacenters · MICRO 2021
Distributed systems
remote procedure call
0.512021
Cerebros: Evading the RPC Tax in Datacenters · MICRO 2021
Datacenter networks
kernel bypass
0.112021
Cerebros: Evading the RPC Tax in Datacenters · MICRO 2021
Internet architecture and protocols › network architecture design › layered architecture › protocol layering
network stack
0.112021
Cerebros: Evading the RPC Tax in Datacenters · MICRO 2021

Methods — techniques the papers use, named apart from their topics

fixed-point arithmetic · 1.0dedicated RPC processor · 1.0batching · 1.0NIC-attached hardware accelerator · 1.0programmable accelerator · 0.4in-memory schema · 0.4
YearPublicationVenuePosition
2021 Equinox: Training (for Free) on a Custom Inference Accelerator
abstract
DNN inference accelerators executing online services exhibit low average loads because of service demand variability, leading to poor resource utilization. Unfortunately, reclaiming idle inference cycles is difficult as other workloads can not execute on a custom accelerator. With recent proposals for the use of fixed-point arithmetic in training, there are opportunities for training services to piggyback on inference accelerators. We make the observation that a key challenge in doing so is maintaining service-level latency constraints for inference. We show that relaxing latency constraints in an inference accelerator with ALU arrays that are batching-optimized achieves near-optimal throughput for a given area and power envelope while maintaining inference services’ tail latency goals.
Mario Drumond, Louis Coulon, Arash Pourhabibi Zarandi, Ahmet Caner Yuzuguler, Babak Falsafi, Martin Jaggi
MICRO3
2021 Cerebros: Evading the RPC Tax in Datacenters
abstract
The emerging paradigm of microservices decomposes online services into fine-grained software modules frequently communicating over the datacenter network, often using Remote Procedure Calls (RPCs). Ongoing advancements in the network stack have exposed the RPC layer itself as a bottleneck, that we show accounts for 40–90% of a microservice’s total execution cycles. We break down the underlying modules that comprise production RPC layers and demonstrate, based on prior evidence, that CPUs can only expect limited improvements for such tasks, mandating a shift to hardware to remove the RPC layer as a limiter of microservice performance. Although recently proposed accelerators can efficiently handle a portion of the RPC layer, their overall benefit is limited by unnecessary CPU involvement, which occurs because the accelerators are architected as co-processors under the CPU’s control. Instead, we show that conclusively removing the RPC layer bottleneck requires all of the RPC layer’s modules to be executed by a NIC-attached hardware accelerator. We introduce Cerebros, a dedicated RPC processor that executes the Apache Thrift RPC layer and acts as an intermediary stage between the NIC and the microservice running on the CPU. Our evaluation using the DeathStarBench microservice suite shows that Cerebros reduces the CPU cycles spent in the RPC layer by 37–64 ×, yielding a 1.8–14 × reduction in total cycles expended per microservice request.
Arash Pourhabibi Zarandi, Mark Sutherland, Alexandros Daglis, Babak Falsafi
MICRO1
2020 Optimus Prime: Accelerating Data Transformation in Servers
abstract
Modern online services are shifting away from monolithic applications to loosely-coupled microservices because of their improved scalability, reliability, programmability and development velocity. Microservices communicating over the datacenter network require data transformation (DT) to convert messages back and forth between their internal formats. This work identifies DT as a bottleneck due to reductions in latency of the surrounding system components, namely application runtimes, protocol stacks, and network hardware. We therefore propose Optimus Prime (OP), a programmable DT accelerator that uses a novel abstraction, an in-memory schema, to represent DT operations. The schema is compatible with today's DT frameworks and enables any compliant accelerator to perform the transformations comprising a request in parallel. Our evaluation shows that OP's DT throughput matches the line rate of today's NICs and has ~60x higher throughput compared to software, at a tiny fraction of the CPU's silicon area and power. We also evaluate a set of microservices running on Thrift, and show up to 30% reduction in service latency.
Arash Pourhabibi Zarandi, Siddharth Gupta 0003, Hussein Kassir, Mark Sutherland, Zilu Tian, Mario Drumond, Babak Falsafi, Christoph Koch 0001
ASPLOS1
2016 Towards near-threshold server processors
Ali Pahlevan, Javier Picorel, Arash Pourhabibi Zarandi, Davide Rossi 0001, Marina Zapater, Andrea Bartolini, Pablo García Del Valle, David Atienza 0001, Luca Benini, Babak Falsafi
DATE3