In the never-ending quest for performance, multicore processors include a variety of hardware-managed performance-improving components. In this paper, we are mostly interested in components pertaining to the memory subsystem, like prefetch queues, caches, or complex arbiters. We study the case where such components generate or take into account memory access bursts. We show how an explicit modeling of memory traffic burstiness allows significant improvements in the precision of interference analysis. We provide both the formal apparatus for modeling burstiness and dedicated analysis algorithms. Evaluation is performed on one of the few high-performance shared-memory architectures that is welldocumented - the Kalray MPPA3 Coolidge many-core, where our method covers one compute cluster.

The increasing complexity of embedded applications in modern cars has increased the need of computational power. To meet this requirement the European automotive standard AUTOSAR has introduced the use of multi-core platforms in it version 4.x. In the industry, the applications are often designed and validated by high level models such as Matlab/Simulink before being implemented on AUTOSAR. However, passing from a Simulink synchronous model to a multi-core AUTOSAR implementation is not trivial. In this paper, we present an approach to model formally the synchronous semantic of any multi-periodic Simulink system by Synchronous Dataflow Graph. Our model is constructed on a formal equivalence between the data dependencies imposed by the communication mechanisms in Simulink and the precedence constraints of a synchronous dataflow graph. The resulting graph is equivalent in size to the Simulink description and allows multi/many-core accurate implementation analysis.