Demo Data from EDBT 2026 / reviewers in the wild / expert
Nitin Shivaraman
dblp:179/3256
· DBLP profile ↗
6ranked-venue papers
6as first author
1since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-authorComputer networks · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
2 papers |
Internet of things and sensor networks · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Distributed systems · 65% Electronic design automation · 35% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Internet of things and sensor networks
time synchronization |
0.9 | 2 | 2021 | Cluster-Based Network Time Synchronization for Resilience with Energy Efficiency · RTSS 2021 Poster Abstract: C-Sync: The Resilient Time Synchronization Protocol · IPSN 2020 |
Internet of things and sensor networks › wireless sensor network
energy-efficient communication |
0.5 | 1 | 2021 | Cluster-Based Network Time Synchronization for Resilience with Energy Efficiency · RTSS 2021 |
Internet of things and sensor networks › reliability
failure resilience |
0.5 | 1 | 2021 | Cluster-Based Network Time Synchronization for Resilience with Energy Efficiency · RTSS 2021 |
Internet of things and sensor networks › security
byzantine fault tolerance |
0.4 | 1 | 2020 | Poster Abstract: C-Sync: The Resilient Time Synchronization Protocol · IPSN 2020 |
Distributed systems
fault tolerance |
0.3 | 2 | 2021 | Cluster-Based Network Time Synchronization for Resilience with Energy Efficiency · RTSS 2021 Poster Abstract: C-Sync: The Resilient Time Synchronization Protocol · IPSN 2020 |
Electronic design automation › hardware verification and test › fault diagnosis
fault detection and isolation |
0.1 | 1 | 2021 | Cluster-Based Network Time Synchronization for Resilience with Energy Efficiency · RTSS 2021 |
Methods — techniques the papers use, named apart from their topics
clustering protocol · 0.9byzantine fault tolerance · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Cluster-Based Network Time Synchronization for Resilience with Energy EfficiencyabstractTime synchronization of devices in Internet-of-Things (IoT) networks is one of the challenging problems and a pre-requisite for the design of low-latency applications. Although many existing solutions have tried to address this problem, almost all solutions assume all the devices (nodes) in the network are faultless. Furthermore, these solutions exchange a large number of messages to achieve synchronization, leading to significant communication and energy overhead. To address these short-comings, we propose C-sync, a clustering-based decentralized time synchronization protocol that provides resilience against several types of faults with energy-efficient communication. C-sync achieves scalability by introducing multiple reference nodes in the network that restrict the maximum number of hops any node can have to its time source. The protocol is designed with a modular structure on the Contiki platform to allow application transitions. We evaluate C-sync on a real testbed that comprises over 40 Tmote Sky hardware nodes distributed across different levels in a building and show through experiments the fault resilience, energy efficiency, and scalability of the protocol. C-sync detects and isolates faults to a cluster and recovers quickly. The evaluation makes a qualitative comparison with state-of-the-art protocols and a quantitative comparison with a class of decentralized protocols (derived from GTSP) that provide synchronization with no/limited fault-tolerance. Results also show a reduction of 56.12% and 75.75% in power consumption in the worst-case and best-case scenarios, respectively, compared to GTSP, while achieving similar accuracy. Nitin Shivaraman, Patrick Schuster, Saravanan Ramanathan, Arvind Easwaran, Sebastian Steinhorst |
RTSS | 1 |
| 2020 | Real-Time Energy Monitoring in IoT-enabled Mobile DevicesabstractWith rapid advancements in the Internet of Things (IoT) paradigm, electrical devices in the near future is expected to have IoT capabilities. This enables fine-grained tracking of individual energy consumption data of such devices, offering location-independent per-device billing. Thus, it is more fine-grained than the location-based metering of state-of-the-art infrastructure, which traditionally aggregates on a building or household level, defining the entity to be billed. However, such in-device energy metering is susceptible to manipulation and fraud. As a remedy, we propose a decentralized metering architecture that enables devices with IoT capabilities to measure their own energy consumption. In this architecture, the device-level consumption is additionally reported to a system-level aggregator that verifies distributed information and provides secure data storage using Blockchain, preventing data manipulation by untrusted entities. Using evaluations on an experimental testbed, we show that the proposed architecture supports device mobility and enables location-independent monitoring of energy consumption. Nitin Shivaraman, Seima Saki, Saravanan Ramanathan, Arvind Easwaran, Sebastian Steinhorst |
DATE | 1 |
| 2020 | DeCoRIC: Decentralized Connected Resilient IoT ClusteringabstractMaintaining peer-to-peer connectivity with low energy overhead is a key requirement for several emerging Internet of Things (IoT) applications. It is also desirable to develop such connectivity solutions for non-static network topologies, so that resilience to device failures can be fully realized. De-centralized clustering has emerged as a promising technique to address this critical challenge. Clustering of nodes around cluster heads (CHs) provides an energy-efficient two-tier framework for peer-to-peer communication. At the same time, decentralization ensures that the framework can quickly adapt to a dynamically changing network topology. Although some decentralized clustering solutions have been proposed in the literature, they either lack guarantees on connectivity or incur significant energy overhead to maintain the clusters. In this paper, we present Decentralized Connected Resilient IoT Clustering (DeCoRIC), an energy-efficient clustering scheme that is self-organizing and resilient to network changes while guaranteeing connectivity. Using experiments implemented on the Contiki simulator, we show that our clustering scheme adapts itself to node faults in a time-bound manner. Our experiments show that DeCoRIC achieves 100% connectivity among all nodes while improving the power efficiency of nodes in the system compared to the state-of-the-art techniques BEEM and LEACH by up to 110% and 70%, respectively. The improved power efficiency also translates to longer lifetime before first node death with a best-case of 109% longer than BEEM and 42% longer than LEACH. Nitin Shivaraman, Saravanan Ramanathan, Shanker Shreejith, Arvind Easwaran, Sebastian Steinhorst |
ICCCN | 1 |
| 2020 | Poster Abstract: C-Sync: The Resilient Time Synchronization ProtocolabstractTime synchronization is paramount for communication in Internet of Things (IoT) networks. Existing synchronization protocols in the IoT are designed to be accurate, energy-efficient and scalable with absolute trust on the time source(s). If a byzantine node becomes a time source, it can cause synchronization errors with false time, leading to system mal-functions or network crashes. In this paper, we introduce C-Sync: a clustering time synchronization protocol for decentralized IoT networks that incorporates resilience against byzantine nodes. We show that C-sync achieves a worst-case synchronization accuracy of a few tens of microseconds (µs). Nitin Shivaraman, Patrick Schuster, Saravanan Ramanathan, Arvind Easwaran, Sebastian Steinhorst |
IPSN | 1 |
| 2017 | Efficient decentralized active balancing strategy for smart battery cellsabstractAmong series-connected cells in large battery packs, such as those found in electric vehicles, a charge imbalance develops over time due to manufacturing and temperature variations. Therefore, active balancing strategies can be employed in Battery Management Systems (BMSs) to attain a charge balance among cells by transferring charge between them, maximizing the usable capacity of the battery pack. Recently, decentralized BMS architectures with smart battery cells have been developed, in which balancing strategies can operate by local cooperation between the cells without requiring global coordination. In this paper, we propose a decentralized active balancing strategy for smart cells where we identify boundary cells having special properties. These boundary cells enable to divide the global balancing problem into independent subproblems, where local decisions on charge transfers eventually converge to a globally balanced battery pack. The proposed strategy is implemented in a simulator framework and compared with two decentralized state-of-the-art strategies. Our results show significantly improved performance and scalability of the proposed strategy in terms of charge transfer losses and communication overhead between cells, while maintaining a comparable time to balance. Nitin Shivaraman, Arvind Easwaran, Sebastian Steinhorst |
DATE | 1 |
| 2016 | Demo Abstract: Predictable SoC Architecture Based on COTS Multi-CoreabstractSummary form only given. With the increasing complexity of real-time embedded applications and the availability of Commercial-Off-The-Shelf (COTS) multi-cores, time-predictable execution on these platforms has become a necessity. However, there are several challenges to achieving this predictability, primarily arising due to hardware resources shared between the cores (memory controllers, caches and shared interconnect). In this demo, we present a novel System-on-Chip (SoC) architecture based on COTS multi-cores that address some of these challenges. Specifically, we develop an architecture that enables COTS multi-cores to predictably access external memory. This SoC is designed using hybrid hardware platforms comprising a COTS multi-core and closely coupled Field Programmable Gate Array (FPGA), e.g., Xilinx Zynq ZC706. In our design, the COTS multi-core (ARM Cortex-A9 dual-core) is integrated using a high-speed interconnect with an arbiter module and the Memory Interface Generator (MIG) Xilinx memory controller on the FPGA. Through experiments we show that the proposed architecture has a precisely predictable worst-case memory access latency when compared to a COTS-only design. Nitin Shivaraman, Sriram Vasudevan, Arvind Easwaran |
RTAS | 1 |