Demo Data from EDBT 2026 / reviewers in the wild / expert
Deepak Kachave
dblp:179/5793
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2019
0000-0003-3181-4835ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
1 paper |
Hardware security and side channels · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
intellectual property protection |
0.4 | 1 | 2019 | Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Hardware security and side channels › hardware obfuscation › logic obfuscation
logic locking |
0.4 | 1 | 2019 | Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Electronic design automation
intellectual property protection |
0.4 | 1 | 2019 | Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2019 |
Methods — techniques the papers use, named apart from their topics
multipairwise secure locking · 0.8IP locking · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust LockingabstractIntellectual property (IP) cores used in consumer electronics devices mandate protection against reverse engineering (RE) attacks. Functional obfuscation protects the design functionality by enhancing the complexity of RE attacks. This paper proposes a novel low cost (based on power-delay tradeoff) functional obfuscation methodology through employment of robust IP locking technique. In the proposed obfuscation methodology, several strong multipairwise secure IP locking block designs are presented that can only be actuated through application of valid serial key bits. As demonstration, this paper also shows a practical example of a functional obfuscated netlist structure of FIR filter. Proposed obfuscation on comparison with a recent approach for several DSP cores yielded a power reduction of ~10%, design cost reduction ~ 6.5% and security enhancement (strength of obfuscation) of $>\,\,4.29\,\,{e+9}$ times. Anirban Sengupta 0003, Deepak Kachave, Dipanjan Roy |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2018 | Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis
Anirban Sengupta 0003, Deepak Kachave |
Future Gener. Comput. Syst. | 2 |