Summary Container virtualization is an emerging technology in cloud computing mainly due to its portability and lightweight features. Scheduling is a key task, performed by container management tool, which indirectly affects the characteristics of distributed software system in terms of availability, realizability, scalability, resources utilization, as well as power consumption. However, current schedulers only focus on some of the aforementioned aspects but not all. In this paper, a Many‐Objective Genetic Algorithm Scheduler (MOGAS) is proposed to handle all such objectives to realize solutions with better characteristics. The proposed scheduler is compared with the Ant Colony Optimization (ACO)–based scheduler. Based on the proposed objective functions, simulation results show that MOGAS is better than the ACO scheduler in equally distributing tasks by 50%, assigning unique set of tasks per node by 40%, and reducing power consumption by 7%, on average.

We present a method for test power reduction in compression-based reconfigurable scan architectures. In addition to their key objective of minimizing Test Data Volume (TDV), we illustrate how the distribution of care bits in scan chains can be manipulated with the objective of reducing the number of transitions during test. Hence, peak and average power of shift and capture operations are effectively reduced.

Disturb failures are considered the most predominant failure mode in flash memories. Disturb faults are highly dependant on the core memory cell structure, manufacturing technology, and array organization and operation. In this paper, we develop appropriate fault primitives for all possible disturb faults in flash memories. Further, we analyze the origins of such disturbs and propose a method that uses cell structure and array organization information to identify the relevant disturbs to create reduced list of faults. As an example, the method was used to create a minimized faults list for NOR and NAND flash memory arrays. Moreover, we show how the reduced fault list developed can be used to devise more efficient test algorithms.

Nonvolatile memories (NVMs) are susceptible to a special type of faults known as program disturb faults. These faults are described using logical fault models and often functional tests are used to detect different faults that occur under such models. The use of functional fault models and tests results in the simplification of the testing process, although such tests can be very long. In this paper, we present a defect-based model that can be used to model different disturb faults in NVM. The relationship between defect location and fault manifestation is first established using electrical simulation. Next, the use of stress tests and margin read schemes and how they are used to detect disturb faults is discussed. Using electrical simulation results, we show that defect-based testing can be used to optimize the cost of program disturb tests of NVM.

Non-volatile memories are susceptible to special type of faults known as program disturb faults. Testing for such faults requires the application of stress tests which have long application time to distinguish faulty cells from non-faulty cells. In this paper we present a new sensing scheme that can be used with stress tests to allow for efficient detection of faulty cells based on the notion of margin reads. We demonstrate the efficiency of the margin-read approach for distinguishing between faulty and fault-free cells using electrical simulations.

Nonvolatile Memories (NVMs) can undergo different types of disturbances. These disturbances are particular to the technology and the cell structure of the memory element. In this paper we develop a coupling fault model that appropriately models disturbances in flash memories that use floating gate transistor as their core memory element. We describe the behavior of faulty cells under different fault models and how their characteristics change under each model. We demonstrate the inappropriateness of conventional march algorithms for testing flash memories and present a procedure to derive pseudo-algorithms that can be used in testing flash memories. In addition we present an efficient test that detects these disturbances under different fault models developed in this paper.