The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads. Finding a feasible worst case workload is difficult due to logical correlation within the logic circuit under consideration. In this article, we propose an NBTI-aware subset simulation (SS) framework that efficiently and accurately finds the failure probability covering various input duty cycles determined by different workloads. In addition, the proposed method is incorporated with the NBTI mitigation technique to facilitate workload-aware mitigation. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to a naive Monte Carlo method. The NBTI mitigation based on SS demonstrates$1.78\times $better mitigation for multiple input duty cycles compared to the conventional method.

The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads, and thus path delay degradation is strongly dependent on each use case. In this paper, we propose a subset simulation (SS) framework that efficiently and accurately finds the worst case workload and the failure probability covering various workloads. In the proposed method, workloads that yield worst aged delay are efficiently generated by the NBTI-aware Markov chain Monte Carlo method. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to the naive Monte Carlo method. From the result of the SS, feasible workload that gives worst aged delay is obtained.

A device array circuit, scalable in terms of the number of transistors used, is proposed. The proposed array facilitates accurate and simultaneous bias voltage application to a large number of devices, making it suitable for the measurement-based statistical characterization of device degradation, known as bias temperature instability. Using the proposed array, the degradation measurement of thousands of transistors is made possible in a practical amount of time. The experimental results show that the defect-centric model can approximate the statistical variation in magnitudes of threshold voltage shifts (ΔVTH) and that the variance of ΔVTHbears an inverse relationship to the channel areas of transistors. The degradation variability under ac stress conditions is also presented for the first time.

As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) is known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, with careful examination, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and proposes a two-stage path extraction algorithm to identify the invariable critical paths in the processor. Through numerical experiment on a MIPS32 processor, we performed a detailed signal probability analysis, and successfully extracted 85 invariable critical paths out of the 24,978 path candidates, achieving nearly 300x reduction in the sheer number of paths.