Diagnosis simulation based on stuck-at faults cannot expose all chain diagnosis problems because silicon defects don’t behave exactly as stuck-at faults. For chain failures, the fault effect can be activated during scan shift cycles and capture cycles in scan test patterns. The activation conditions of silicon defects are generally more complex and do not activate the fault effect in all cycles. To accurately estimate diagnosis coverage during chain diagnosis simulation, this paper proposes using distinguishing bits. Distinguishing bits, which are simulation-failing bits of one fault but not simulation-failing bits of another fault, are used in this paper to distinguish each silicon defect from others. The chain diagnosis quality of silicon defects can be improved by increasing the distinguishing bits of all scan cell faults. Specific diagnosis test patterns are proposed to increase the number of distinguishing bits of each fault. If the diagnosis test patterns cannot be created, adaptive diagnosis points are proposed to modify the designs to facilitate the creation of these diagnosis test patterns.

As process geometry shrinks, the complexity of transistors in electrical devices have also increased exponentially. Silicon devices manufactured with these new processes are used in safety-sensitive products. Reliability is, therefore, an extremely important factor in such devices. High quality test and screening are a requirement during production of such devices. In this paper, we present a new methodology for advanced nodes like 3nm that include high quality test patterns to improve screening of defective parts and, scan diagnosis to achieve improved physical failure analysis resolution. In particular, the new scan diagnosis methodology presented in this paper improved defect identification especially in global control signal networks over previous techniques. Experimental results shown in the paper demonstrates the uncovering of real systematic defects that were encountered in silicon production at Samsung Foundry.

Scan diagnosis has long been relied upon to provide localized defect suspects for a failing die using failing test cycle information for that die and design data. These suspects from scan diagnosis have been used to drive failure analysis (FA) to find the root cause of manufacturing yield loss. The fewer suspects that scan diagnosis produces (higher diagnosis resolution), the quicker and more efficient the FA cycle time. The gains observed are mainly due to the reduced need for fault isolation for these highly resolved diagnosis reports. Identifying design or test pattern related bottlenecks to diagnosis resolution earlier in the design cycle can be useful to anticipate the impact of a particular design on yield learning. In the technique described in this paper, we show how diagnosis resolution can be estimated from design data for both chain and logic defects. The detailed comparison of diagnostic metrics and resolution statistics from simulation and silicon results are presented. Overall, we observe strong correlation in the predicted resolution metrics and diagnosis quality.

We will show the real implementation of a very high test compression scheme for a 3 pin image sensor device. This new approach results in achieving the same compression ratio of 27.7X and the same test coverage on 3 pins instead of 8 pins for a typical scan design.