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Thomas Thomas

dblp:18/1213 · DBLP profile ↗
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5ranked-venue papers
1as first author
0since 2021 · last 2014
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorArtificial intelligence and machine learning · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Distributed systems · 61% High-performance computing · 30% Cloud and datacenter computing · 9%
Software engineering, system software, and programming languages
1 paper
Services computing and microservices · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Services computing and microservices
web services
0.112005
Building Grid Portal Applications From a Web Service Component Architecture · Proc. IEEE 2005
Distributed systems
grid computing
0.112005
Building Grid Portal Applications From a Web Service Component Architecture · Proc. IEEE 2005
Distributed systems › grid computing
science gateway
0.112005
Building Grid Portal Applications From a Web Service Component Architecture · Proc. IEEE 2005
High-performance computing
scientific workflow
0.112005
Building Grid Portal Applications From a Web Service Component Architecture · Proc. IEEE 2005
Cloud and datacenter computing
resource management
0.012005
Building Grid Portal Applications From a Web Service Component Architecture · Proc. IEEE 2005

Methods — techniques the papers use, named apart from their topics

workflow composition · 0.1service wrapping · 0.1
YearPublicationVenuePosition
2014 Collecting Natural SMS and Chat Conversations in Multiple Languages: The BOLT Phase 2 Corpus
Zhiyi Song, Stephanie M. Strassel, Haejoong Lee, Kevin Walker, Jonathan Wright, Jennifer Garland, Dana Fore, Brian Gainor, Preston Cabe, Thomas Thomas, Brendan Callahan, Ann Sawyer
LREC10
2005 Building Grid Portal Applications From a Web Service Component Architecture
abstract
This work describes an approach to building Grid applications based on the premise that users who wish to access and run these applications prefer to do so without becoming experts on Grid technology. We describe an application architecture based on wrapping user applications and application workflows as Web services and Web service resources. These services are visible to the users and to resource providers through a family of Grid portal components that can be used to configure, launch, and monitor complex applications in the scientific language of the end user. The applications in this model are instantiated by an application factory service. The layered design of the architecture makes it possible for an expert to configure an application factory service with a custom user interface client that may be dynamically loaded into the portal.
Dennis Gannon, Jay Alameda, Octav Chipara, Marcus Christie, Vinayak Dukle, Matthew Farrellee, Gopi Kandaswamy, Deepti Kodeboyina, Sriram Krishnan, Charles W. Moad, Marlon E. Pierce, Beth Plale, Albert L. Rossi, Yogesh L. Simmhan, Anuraag Sarangi, Aleksander Slominski, Satoshi Shirasuna, Thomas Thomas
Proc. IEEE19
1994 Impact of behavioral modifications for testability
abstract
Behavioral specification of a VLSI design can be used to suggest behavioral modifications that improve testability of the design. Past work has been targeted at identifying the techniques that will enable such modifications. However, the impact of such behavioral modifications on the testability of a design has not been analyzed with regards to fault coverage and area overhead which is the focus of this paper. Results obtained show that the area overhead is low and the fault coverage is higher when the behavior is modified for testability. These results are compared with the results obtained when partial scan is used to improve the testability of a design.>
Thomas Thomas, Praveen Vishakantaiah, Jacob A. Abraham
VTS1
1993 A Comparative Evaluation of Adders Based on Performance and Testability
abstract
Testability is becoming an increasing concern in the design of present-day VLSI systems because of their higher density and complexity. This is particularly important in the case of arithmetic units, such as adders, which form the core of any processing unit. Techniques like design for testability (DFT) have been implemented, but a methodology for evaluating and selecting a suitable adder has not been developed. We present an exhaustive comparison of adders in terms of performance, area and testability, by formulating a figure of merit, the PLUS factor. The results of this comparison can be extended to evaluate the suitability of an adder for a particular set of design goals and constraints.>
Rathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr.
ICCD2
1993 AMBIANT: Automatic Generation of Behavioral Modifications for Testability
abstract
The paper discusses techniques that help a designer to consider testability features early in the design cycle. The behavioral specification of a design is used to perform high level testability analysis, based on which behavioral modifications for testability are suggested to the designer. Results show that the overhead for incorporating these modifications is minimal.>
Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir
ICCD2