Extended classifier systems (XCS) suffer from suboptimal performance when the optimal classifiers of the functions they deal with overlap. As this overlap is the property of Boolean functions and the generalization capabilities of the ternary alphabet {0,1,#}, it is necessary to improve XCS to better deal with those functions that make up most of the possible Boolean functions. This paper proposes two techniques that improve XCS performance, both in terms of system and population state metrics. The first technique, termed Essentiality Assessment, alters the current fitness update mechanism by disallowing competition between potentially essential classifiers. The second technique, named Individualized Learning Rate, proposes an individually computed learning rate for each classifier based on the level of generality of each classifier. The results obtained show improvement and significance both in absolute and statistical terms, for the vast majority of system and population state metrics. This paper is a contribution toward improving XCS performance when dealing with single-step problems that necessarily require overlapping classifiers for their optimal solution.

In this paper we applied the eXtended Classifier System (XCS) on a novel real world problem, namely digital Design Verification (DV). We witnessed the inadequacy of XCS on binary problems that contain high overlap between optimal rules especially when the focus is on population and not system level performance. The literature attempts to underplay the importance of the aforementioned weakness and in short, supports that a) XCS can potentially learn any Boolean function given enough resources are allocated (right parameters used) and b) the main metric deciding the learning difficulty of a Boolean function is the amount of classifiers required to represent it (i.e. |[O]|). With this work we experimentally refuted the aforementioned propositions and as a result of the work, we introduce new insights on the behavior of XCS when solving two-valued Boolean functions using a binary reward scheme (1000/0). We also introduce a new population metric (%[EPI]) that should necessarily be used to guide future research on improving XCS performance on the aforementioned problems.

Getting the interlock logic which controls pipeline flow correct is an important prerequisite for maximising pipeline performance. Unnecessary pipeline stalls can only be eliminated when they can be distinguished from those stalls which are necessary to preserve functional correctness. Typically, designers know when these necessary stalls should occur.We propose a method for deriving a maximum pipeline performance specification from a complete functional specification of the pipeline control logic. The performance specification can be used to generate simulation testbench assertions. On the other hand, the specification can serve as a basis for formal property checking. The most promising aspect of our work is, however, the potential to synthesise the actual control logic from its formal description.

Article Functional verification methodology of Chameleon processor Share on Authors: Françoise Casaubieilh Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Anthony McIsaac Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Mike Benjamin Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Mike Bartley Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , François Pogodalla Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Frédéric Rocheteau Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Mohamed Belhadj Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Jeremy Eggleton Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Gérard Mas Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Geoff Barrett Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile , Christian Berthet Chameleon Programme, SGS-THOMSON Microelectronics Chameleon Programme, SGS-THOMSON MicroelectronicsView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 421–426https://doi.org/10.1145/240518.240599Online:01 June 1996Publication History 23citation408DownloadsMetricsTotal Citations23Total Downloads408Last 12 Months5Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

One of the major obstacles to the integration of formal methods in the design of industrial products is the height and gradient of the learning curve, Anything which can alleviate this problem is of enormous benefit. Automatic model checking and visual specification styles provide a gentle introduction to the concept of refinement. The paper presents a case study of the design of the T9000 virtual channel processor as an illustration of the use of some nonstandard CSP operators and a visual specification style. The development which is shown here has been implemented in a single model checking tool which is currently being integrated into the INMOS CAD system.>

Abstract This paper presents a fixed point theorem for the infinite traces model of CSP. Unlike any other model of CSP, there is no complete partial order over the infinite traces model whose fixed point theory agrees with the operational semantics (A. W. Roscoe, Oxford University Computing Laboratory Technical Monograph PRG-67, 1988). This arises from the introduction of unbounded non-determinism. However, the subset of pre-deterministic processes, that is those which describe the behaviour of a process on some run of its implementation, do form a subset for which the usual order is complete. By requiring that each CSP operator has a monotonic implementation which preserves pre-determinism, it is possible to show that all CSP operators have a least fixed point. In effect, it is the requirement that all operators have a methodical implementation.

A formalization of the IEEE standard for binary floating-point arithmetic (ANSI/IEEE Std. 754-1985) is presented in the set-theoretic specification language Z. The formal specification is refined into four sequential components, which unpack the operands, perform the arithmetic, and pack and round the result. This refinement follows proven rules and so demonstrates a mathematically rigorous method of program development. In the course of the proofs, useful internal representations of floating-point numbers are specified. The procedures presented form the basis for the floating-point unit of the Inmos IMS T800 transputer.>

This paper presents a formal description of rounding, as specified in the IEEE Standard, and an algorithm to perform the task along with its proof of correctness.