This paper demonstrates a 12-bit 100-MS/s PVT-stabilized pipelined-SAR ADC with fully integrated on-chip calibration. Two key innovations facilitate over 65-dB SNDR with less than 2.2-dB variation from -20 °C to 125 °C: First, a PVT-stabilized nested negative-C topology boosts open-loop gain ($G_{ol}$) of the residue amplifier (RA) by 28 dB, enabling one-time foreground calibration that avoids persistent inter-stage gain error tracking. Second, a dynamic auto-zeroing technique addresses offsets from both the RA and first-stage comparator through a switched-capacitor filter that extracts offsets based on the stochastic characteristics of residue signals. Dynamically level-shifted capacitors (DLSC) are embedded at the differential inputs to neutralize aliased noise and thermal noise, so that the offset drifts under high-temperature environment are effectively cancelled. Fabricated in 40-nm CMOS, the prototype occupies 0.22 mm2and achieves 65.5-dB SNDR and 83-dB SFDR at Nyquist input while consuming 3.7 mW. Across six tested chips, the prototype design exhibits merely 2.2-dB SNDR degradation over -20 °C ~ 125 °C and 1.3-dB variation under ± 5 % supply voltage (1.1 V) fluctuations.

This article presents a 5-GS/s 8-bit single-channel hybrid analog-to-digital converter (ADC) with a$\lambda $/4 transmission line (T-Line) based time-to-digital converter (TDC). Taking advantage of the traveling wave technique, the T-Line based TDC breaks the time step (TLSB) limitation caused by jitter tolerance and process, voltage, and temperature (PVT) variations. An improved bootstrapped generator for the input switch enables rapid start-up and reduces tracking time, accommodating the high sampling rate. Fabricated in a 28-nm CMOS technology, the prototype ADC core consumes 19.8 mW at 5 GS/s with a 0.9-V supply. It achieves a signal-to-noise and distortion ratio (SNDR) of 38.04 dB with a Nyquist input, corresponding to a Walden figure-of-merit of 60.7 fJ/conv-step. The measured variation in SNDR is below 0.34 dB across temperature variation of$- 25~^{\circ }$C to$125~^{\circ }$C, and below 0.74 dB over supply variations of ±5%.

This paper presents a fully integrated reconfigurable single-channel IC with high energy efficiency for bio-signal acquisition in Internet-of-Medical Things (IoMT) systems. The overall signal chain consists of a capacitively-coupled instrumentation amplifier (CCIA) and a 16-bit delta-sigma ($\Delta$$\Sigma$) ADC. The ADC is directly driven by the CCIA without a traditional driver stage. The folded path of the first stage in CCIA is sliced for reconfigurable noise levels. In addition, a single-stage floating inverter amplifier (FIA) assisted by the correlated-level-shifting (CLS) technique is employed in the switched-capacitor (SC)$\Delta$$\Sigma$modulator for fully dynamic operation with sufficient DC gain. Fabricated in 180-nm CMOS, the CCIA achieves an input-referred noise level ranging from 35.8 to 67 nV/$\surd$Hz with a best noise-efficiency factor (NEF) of 5.54. It corresponds to an integrated noise ranging from 0.63 to 1.16$\mu$$\text{V}_\text{rms}$(0.5-100 Hz) and 1.93 to 3.51$\mu$$\text{V}_\text{rms}$(0.1-3 kHz), respectively. The ADC achieves a peak SNDR of 92.6 dB for a 2.3-$\text{V}_\text{pp}$differential input and can support 16$\times$power/BW reconfigurability with ENOB$>$15 bit. The complete system occupies an active area of 0.56 mm$^{2}$and achieves 85.7-dB system SNDR over a 500 Hz BW with an OSR of 128. It consumes 36.8$\mu$W from a 1.8-V supply, corresponding to an SNDR-based Schreier FoM of 157 dB. Biological measurement is demonstrated successfully, and the results verify that the proposed IC is applicable to high-quality ExG signal acquisition.

This paper presents a digital background timing-skew calibration technique with high accuracy and bandwidth in time-interleaved (TI) analog-to-digital converters (ADCs). Compared with other calibration works, it features three highlights. Firstly, the proposed DCSD-based step-by-step and grouping calibration scheme can effectively improve the correction accuracy by minimizing the root mean square (RMS) value of the detected timing skews. Secondly, the linear compensation for a 13-taps FIR filter and the decimation-calibration-interpolation working pattern are used to expand the calibration effective bandwidth to the whole first Nyquist zone from different perspectives. Thirdly, the binary search is employed, instead of LMS algorithm, in order to meet the compensation requirement for FIR filter and improve the convergence speed and accuracy significantly in timing-skew detection. As a result, the proposed technique achieves the widest calibration bandwidth and higher accuracy compared to other fully digital calibration techniques while having the great convergence speed. Simulation model in MATLAB and FPGA-based hardware verification are employed to demonstrate its significant improvement on the performance and hardware overhead of the TI-ADCs. Finally, the proposed technique is employed in a 10-bit 2.5 GS/s 4-way TI-SAR ADC fabricated by standard CMOS 28nm process. The measurement results show that with the proposed technique, the SFDR and SNDR are improved by 18.9 and 17.9 dB at Nyquist frequency, respectively.

This paper introduces a dual main clock generator (DMCG) and a digital serializer (DS) to improve the power efficiency of the time-interleaving (TI) analog-to-digital converters (ADCs). The proposed DMCG combines a dual-path front end and an improved selecting signal generator that addresses the potential phase error and reduces the peak current of the clock-driving circuits by 60%. The DS is proposed to serialize the digital outputs without employing power-hungry inverter-based buffer chains thus reducing the power consumption by 39.2%. The reference-free time skew extraction algorithm (RFA) is presented to mitigate the accuracy deterioration due to selecting the fixed middle channel. These techniques are validated by a prototype 12-bit 10-GS/s TI pipelined successive approximation register (TI-Pi-SAR) ADC. Fabricated in a 28-nm CMOS process, the prototype chip occupies an area of 4.4 mm2. The measurement results show that the ADC achieves a 49.8 dB SNDR and 60.0 dB SFDR after calibration at Nyquist frequency, while the total power consumption is 270 mW, leading to the figure of merits of Schreier (FoM$_{\mathrm {S}}$) and Walden (FoM$_{\mathrm {W}}$) of 152.5 dB and 106.9 fJ/conv.-step, respectively.

This article presents a fully dynamic switched-capacitor zoom ADC with 1st-order interstage leakage shaping (ILS). Noise shaping capability is integrated into the coarse stage by a low-cost error-feedback (EF) path, effectively mitigating quantization noise leakage in the traditional zoom architecture due to the non-unity STF. In addition, a swing-enhanced floating inverter amplifier (FIA) architecture is proposed for improved linearity as well as fully dynamic operations. The prototype ADC is fabricated in a 65-nm CMOS process and occupies an active area of 0.22 mm2. With a 1.2-V supply, it achieves 98.1-dB peak SNDR over a 20-kHz bandwidth with 142.8$\mu $W power consumption, resulting in a DR-based Schreier FoM of 182.9 dB and an SNDR-based FoM of 179.5 dB, respectively. According to the measurement results, 8$\times $power/BW configurability can be achieved by the zoom ADC while maintaining SNDR above 98 dB.

A highly linear input buffer is crucial for high-speed and high-resolution analog-to-digital converters (ADCs) since it isolates the kickback noise and package inductance. Several important factors affecting the linearity of the input buffer are analyzed in this brief, and a wideband input buffer with high linearity based on cascade complementary source follower (CCSF) is proposed. This cascaded input buffer is composed of a pMOS source follower (PSF) and an nMOS source follower (NSF). Compensation capacitor, assisted operational amplifier (opamp), bootstrapped-capacitor level-shifting circuit, current amplifier, and optimization strategies are utilized to extend the bandwidth and reduce distortion. Designed in a 65-nm CMOS, the CCSF input buffer achieves the spurious-free dynamic range (SFDR) and a signal-to-noise and distortion ratio (SNDR) of 76.6 and 58.1 dB with 1.9-GHz input frequency, respectively. It occupies 0.0155 mm$^2$and consumes 27 mW at 2.5 V.

This paper presents a 13-tap FIR filter and an IIR filter embedded in a 10-bit SAR ADC for wireless communications chip. The IIR filter can be inherently realized through reusing the capacitor array of the SAR ADC, thus improving the stopband suppression and shaping the transition band. Besides, the DC attenuation is also avoided. The sampling rate loss of the SAR ADC can be compensated by the$4\times $time-interleaving technology. The proposed filter features high power-efficient, linearity and process compatibility. Compared with a 15-tap FIR filter, the out-of-band suppression at the cut-off frequency (OOBS@$f_{\mathrm {cut-off}}$) is enhanced by 9dB theoretically. A prototype FIR/IIR filter in 40nm CMOS occupies an active area of 0.067mm2, consumes$38~\mu \text{W}$at a single supply of 1.1V, has a 1-MHz bandwidth, obtains$>$42.2dB [email protected] when operated at 40MS/s. Meanwhile, the SAR ADC without/with the proposed filter can achieve a FoMw of 7.91 fJ/conversion-step and 13.5 fJ/conversion-step, respectively.

This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time domain, the compact interpolation-based time-to-digital converter (TDC) resolves 4-bit in each SAR cycle with$16\times $linear TD interpolation. This scaling-friendly architecture reduces the number of capacitive digital-to-analog converters (CDACs) and voltage-to-time converters (VTCs) significantly, leading to low power, small area, low kickback noise, and small input loading. A cascade current-starved inverter based VTC is used in the second SAR conversion cycle, which improves voltage-to-time gain and ensures speed and linearity. Besides, to reduce the TD interpolation error and eliminate the short-circuit current, a novel phase interpolator is proposed. A two-way time-interleaved 7-bit 3.8-GS/s prototype ADC was fabricated in a 28-nm CMOS, occupying an active area of 0.01 mm2. With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.9 and 50.8 dB, respectively. Consuming 7.5 mW at 1.0 V supply, the Walden figure of merit (FoMw) is 24.4 fJ/conversion-step.

This paper presents a coarse-fine bypass window technique to improve the energy efficiency of the successive approximation register (SAR) analog-to-digital converter (ADC) by skipping unnecessary conversion cycles when the input signal is within the bypass windows. It utilizes the time information of the MSB comparison to coarsely detect the input range without a dedicated timing budget. Based on the coarse detection results, the fine bypass window is configured by reusing the digital-to-analog converter (DAC) to accurately detect the input signal. Due to the presence of the coarse detection, the multi-window detection and its corresponding bypass operation are realized to maximize the effectiveness of the bypass window technique. In addition, the MSB-spilt switching scheme is proposed to reduce the DAC switch-back energy. A prototype 8-bit SAR ADC equipped with the proposed technique is fabricated in a 65-nm CMOS process. At a 350-MS/s sampling rate with a Nyquist input, the measured signal-to-noise-plus-distortion ratio (SNDR) and spurious-free dynamic ranges (SFDR) are 44.9 dB and 63.9 dB, respectively. At a supply voltage of 1.2 V, the ADC consumes power of 1.58 mW with the full-scale sinusoidal input signal. The ADC achieves an effective number of bits (ENOB) of 7.17 bit, resulting in a figure-of-merit (FoM) of 31.3 fJ/conversion-step. The ADC core occupies an active area of 0.0096 mm2.

This brief presents an 8-bit two-step successive approximation register analog-to-digital converter (SAR ADC), where the interstage gain is embedded in the second-stage comparison to eliminate the dedicated residue amplifier and its timing cost. Combined with the passive residue transfer technique, the prototype ADC realizes high speed while requiring small overhead. Fabricated in 28-nm CMOS, it operates at 1.5 GS/s and achieves an signal-to-noise-and-distortion-ratio (SNDR) of 43.3 dB at Nyquist rate while consuming 2.32 mW, resulting in a Walden figure-of-merit (FOM) of 12.9 fJ/conv-step.

This brief presents a single-channel 8-bit 1.5-GS/s voltage–time (V-T) hybrid two-step analog-to-digital converter (ADC). Benefiting from the fine quantification in the time domain, the power-to-noise requirement of a comparator and speed limitation in the voltage domain have been significantly relaxed. An efficient cross-coupled linearized technique (CCLT) is proposed in a dynamic voltage-to-time converter (VTC) design as a crucial part of this ADC. This technique helps improve the total harmonic distortion (THD) of VTC by 8 dB across most process–voltage–temperature (PVT) variations by avoiding using a power-harvest current-source (CS)-based VTC. Moreover, a dynamic conversion strategy is proposed in a time quantizer to build a more power-efficient design. Fabricated in a 28-nm CMOS process, the prototype ADC consumes 3.3 mW at 1-V supply with an active area of 0.0035 mm2. With a Nyquist input, it achieves a signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 45.4 and 60.3 dB, respectively, yielding a Walden figure of merit (FoMW) of 14.4 fJ/conversion-step.

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW,includingon-chip reference buffers.

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

This brief presents a digital background calibration technique for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs). It updates the calibration step adaptively based on the detection error. This results in large update step initially, and it reduces with the calibration cycle going on. More than two times convergence time is saved compared with the conventional fixed update step method. Besides, by extending the compensation to second-order, both calibration range and accuracy are improved. To demonstrate the effectiveness of the proposed timing skew calibration, extensive simulation and measurement results are provided. It shows that after timing skew calibration, the signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of a two-channel prototype TI ADC are improved by 8.2 and 14.9 dB, respectively.