In-Memory Computing (IMC) has emerged as one of the most promising architectures to efficiently compute artificial intelligence tasks on hardware, particularly Deep Neural Networks (DNNs). IMC can make use of analog computation principles alongside emerging Non-Volatile Memory (eNVM) technologies, potentially offering several orders of magnitude increased energy efficiency compared to generic processing units. Yet, the use of analog circuitry, potentially integrated with emerging technologies post-processed on top of silicon wafers, increases the susceptibility of hardware to a large spectrum of variations, for instance manufacturing, noise or temperature sensitivity. Hence, this susceptibility can hamper the large-scale deployment of IMC circuits into the market. To tackle the reliability of analog resistive-based IMC circuits regarding temperature variations, this paper presents TRIM, a thermal on-chip auto-compensation method aimed at fully calibrating first-order temperature effects. TRIM is designed to maintain the computational accuracy of IMC cores in DNN applications over a wide temperature range, while being highly scalable and adaptable. In essence, the temperature compensation is realized through a Complementary-To-Absolute-Temperature (CTAT) voltage reference integrated inside a voltage regulator and applied at the zero reference node of a Multiplying Digital-to-Analog Converter (MDAC), eliminating the need for external circuits or look-up tables. The proposed methodology is demonstrated on a proof-of-concept 65 nm CMOS resistive IMC column. Measurement results showcase that the proof-of-concept auto-compensation system significantly enhances inference and Multiply-And-Accumulate (MAC) operation accuracy of any first-order resistive crossbar column, achieving inference accuracy recovery of 100% over a temperature range of -20 ∘C to 60 ∘C and a 91.3 in MAC operation accuracy, with an area overhead of 2% and power overhead of <0.02%.

This work presents a sub-100 nW all-in-one voltage and current reference circuit implemented using 600 nm indium gallium zinc oxide (IGZO) thin-film transistor (TFT) on a flexible substrate. The proposed design integrates both voltage and current references into a single, simple, and compact architecture. By employing NMOS-only devices with negative feedback, the circuit achieves temperature compensation over a temperature range from 10 °C to 100 °C through a stabilized zero temperature coefficient (ZTC) bias point, enhancing the temperature coefficients (TCs). Simulation results demonstrate that the circuit provides a stable reference current of 78.14 nA and a reference voltage of 1.153 V at room temperature (27 °C), with TCs of 99.6 ppm/°C and 263.6 ppm/°C, respectively. The line sensitivities (LS) are 1.276%/V for the current reference and 0.319%/V for the voltage reference over a supply voltage range from 1.5 V to 5 V making it suitable for integration into both flexible electronics and even conventional Si-based CMOS circuits. The circuit achieves a current efficiency of 99.95% and occupies an area of 0.0183 mm2.

As the global population ages, caregivers encounter significant challenges in monitoring wet diapers and assessing the volumes of voided fluids in adult incontinence products. Recent advancements in smart-diaper technology address these issues, but challenges persist with integrating electronics, frequent removal and reapplication, and managing batteries. This study presents a batteryless urine-powered IoT sensor node using printed energy harvesters and capacitive sensors integrated with an ultra-low-power integrated circuit for disposable smart diapers. Coplanar capacitive sensors and electrochemical energy harvesters are printed on the flexible substrate using environment-friendly materials. An ultra-low power frontend interface is developed, which is powered by the harvested energy from urine. Laboratory measurements validate the functionality of on-chip electronics and the performance of in-diaper sensors and energy harvesters. The system demonstrates effective energy harvesting by maintaining a stable regulated voltage of 1.1 V with urine volumes of 90 ml or more, powering the front-end electronics continuously for 6 hours. The proposed system successfully demonstrated the detection of multiple urination events in the diaper and quantified the voided volume as low as 30 ml. The results demonstrated in this work pave the way for cost-effective, disposable, and environmentally friendly solutions for smart diapers, enhancing both efficiency and comfort for caregivers and elderly individuals.

In-memory computing (IMC) accelerators have become a pivotal architecture for enhancing AI algorithm computations, particularly critical for embedding deep neural networks (DNNs) in edge devices. The efficiency of these systems is paramount, yet IMC cores are prone to fluctuations due to process, temperature, and voltage variations, which can detrimentally impact DNN accuracy. This research introduces an innovative Built-In Self-Calibration (BISC) methodology, specifically designed to compensate for temperature-induced variations in mixed-signal IMC cores. The methodology enables real-time, on-chip adjustment of DNN weights during computation within the IMC core without modifying the computation path. The proposed approach, implemented on a silicon prototype, not only maintained DNN computation accuracy under substantial temperature variations but also fully compensated for almost 90% of the offset caused by these variations, without introducing any non-idealities.

This work presents a versatile all-NMOS circuit with dual functions, i.e. either as a conventional temperature sensor or as a precise voltage reference, meeting the vital demand for multi-functional, reusable circuits, thus reducing chip area and power consumption constraints. The circuit can measure temperature in one mode and guarantee the reliable function of implants/wearables by delivering a temperature invariant stable reference voltage in the other mode. The circuit works for a wide temperature range of -40°C to 80°C, without needing extra circuits such as operational amplifiers, startup circuits, or resistors. Implemented in a 65 nm bulk CMOS technology, the circuit occupies an area of 0.00393 mm2. The mode of operation can be controlled by a mode control bit. In voltage reference mode, the circuit has a low temperature coefficient of 96 ppm/°C with an output voltage of 604.3 mV at room temperature. The line sensitivity of the circuit is 0.397 %/V in the operation range of 0.7 V to 1.2 V, consuming a power of 21.23 nW. In the temperature sensing mode, the circuit consumes a power of 42.75 nW, with a temperature inaccuracy of +0.929°C/-1.42°C.

In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.

In-Memory Computing (IMC) accelerators based on resistive crossbars are emerging as a promising pathway toward improved energy efficiency in artificial neural networks. While significant research efforts are directed toward designing advanced resistive memory devices, the nonidealities associated with practical device implementation are often overlooked. Existing solutions typically compensate for these nonidealities during off-chip training, introducing additional complexities and failing to account for random errors such as noise, device failures, and cycle-to-cycle variability. To tackle this challenge, this work proposes a self-calibrated activation neuron topology that offers a fully online non-linearity compensation for IMC accelerators. The neuron merges multiply-accumulate operations with Rectified Linear Unit (ReLU) activation function in the analog domain for increased efficiency. The self-calibration is integrated into the data conversion process to minimize overheads and be fully online. The proposed activation neuron is designed and simulated using 22 nm FDSOI CMOS technology. The design demonstrates robustness across a wide temperature range (-40°C to 80°C) and under various process corners, with a maximum accuracy loss of 1 LSB for an 8-bit activation accuracy.

In this paper, we compare in a new way the energy efficiencies of modulations that have been popular in ultra-low power (ULP) transmitters. The comparison considers how the choice of modulation affects the combined energy consumed per bit (EPB) by the carrier synthesizer and power amplifier (PA). The comparison includes on-off keying (OOK), binary phase-shift keying (BPSK), binary frequency-shift keying (BFSK), pulse-position modulation (PPM) and differential PPM (DPPM). The results suggest that using OOK, BPSK or BFSK can consume tens to hundreds of percents more energy per bit compared to PPM and DPPM. Furthermore, a new energy efficiency figure of merit (FOM) is derived for transmitters. It accounts for consumed power, output power, data rate, signal bandwidth and signal-to-noise ratio required by the utilized modulation. The FOM can be applied to various types of transmitters with numerous modulations. We also present a sub-100$\mu \text{W}$DPPM transmitter (TX) and a 3.2-$\mu \text{W}$2-axis gesture sensor interface, implemented in 0.18$\mu \text{m}$CMOS. The TX operates in the 433-MHz band, uses pulse shaping for improved spectrum and achieves a FOM of −189.7 dBJ/bit. The estimated uplink range is up to 1 kilometer.

This paper presents a high dynamic range E-band power detector in a 0.13 μm SiGe BiCMOS technology. In this design the Meyer topology using bipolar transistor is adopted and implemented for E-band operation. The measured detector achieves a dynamic range of 35 dB from -25 dBm to +10 dBm. It shows less than 1.6 dB offset in input power detection from 72 GHz to 82 GHz. This power detector consumes 0.6 mW of DC power and the occupied core area is 0.1 mm2.

Weareable biomedical devices make it possible to monitor physiological parameters of human beings where physical fitness is critical for their work. However, the motion artifacts corrupt the ambulatory measurements of electrophysiological parameters and it is necessary to detect and eliminate these motion artifacts. The long term measurement and analysis of health parameters require enormous data processing and storage resources on board. It is also challenging to perform sensor fusion of multiple devices and to manage multiple communication channels. This paper describes the development of a wearable hardware platform to measure electrocardiogram (ECG) and electromyogram (EMG) with an additional IMU sensor to detect the motion artifacts. Bringing all the sensors on single platform resolves the sensor fusion problems. The measurements are digitized and sent wirelessly through a bluetooth interface to a remote unit in real-time. Which is capable for the implementation of extensive processing and analysis algorithms to detect the motion artifacts and extract The features of ECG and EMG waveform structures.

This paper presents a fully integrated ultra-wideband impulse radio transmitter front-end (TFE) that is compliant with the European spectral mask. The compliance is achieved by means of 4-bit digital pulse shaping and an integrated matching network. The center frequency of the TFE is digitally tunable with 24 MHz resolution between 6.5-8.0 GHz. The TFE delivers at least 2.0 pJ pulses over the whole frequency range and achieves 4.4 % efficiency at 7.5 GHz center frequency and 4 MHz pulse repetition rate. The static power consumption is 480 nW, which enables the TFE to reach high efficiency levels even at low pulse repetition rates. The TFE is designed in a commercial 65-nm CMOS process. The performance of the TFE is evaluated through post-layout simulations.

This paper presents an ultra-low power, wide-dynamic-range interface circuit for capacitive and resistive sensors. It is implemented as a switched-capacitor circuit using tunable capacitors to achieve high configurability. The circuit was fabricated using a 0.18μm CMOS technology. Measured results show that the circuit is able to interface various sensors within the overall capacitance range of 0.6-550pF and resistance range of 3.7kΩ-5.1MΩ, while consuming only 0.39-3.56μW, from a 1.2V supply.

This paper presents a single-stage CMOS narrowband transmitter front-end for the 433-MHz band for low-power applications. The architecture utilizes an off-chip copper loop both as an inductor in a digitally controlled LC oscillator and a radiating element. The carrier frequency can be tuned using on-chip capacitors in steps smaller than 130 kHz over a 141-MHz tuning range. Measured current consumption, drawn from a 1.2-volt supply, is 315 μA and 2.7 nA during on-time and off-time, respectively. Approximate power of the radiated carrier signal is -27 dBm during continuous wave transmission. Due to a fast start-up time and low leakage, the front-end supports well data rates up to 5 Mbps and low-power modulation schemes where the carrier need not be generated all the time e.g. on-off keying (OOK), pulse-position modulation (PPM) and differential pulseposition modulation (DPPM).

This paper presents a versatile, FCC compliant ultra-wideband impulse radio transmitter front-end (TFE) that performs well at a wide range of pulse repetition rates up to 105 MHz. The TFE delivers 2.2 pJ pulses with 6.7 % efficiency at 3.8 GHz center frequency. The leakage power is 180 nW from a 1.2 V supply. The TFE operates robustly with a variety of power sources, including a 6.5 cm2 photovoltaic array in office illumination. Along with the low static power consumption level, this feature makes the TFE suitable for energy harvesting applications. The TFE is fabricated in a 180 nm CMOS process.

This paper presents a 2-axis gesture sensor interface that consumes 462 nW powered by a 0.8 V supply. The system consists of two proximity sensor (PS) interfaces that provide digital data outputs. A single PS interface consists of a capacitively controlled ring oscillator (CCRO) whose frequency is sensitive to the capacitance between two copper plates in a coplanar deployment and additional capacitive load introduced by the presence of a hand. The CCRO in each interface is followed by a modified cascaded integrator comb (CIC) filter that performs the frequency-to-digital conversion, filtering and downsampling. When a total of three sensor plates are arranged in parallel, the middle one acting as a shared ground plate, the location of a user's hand can be obtained in two dimensions. Measurement results show that hand sweep gestures at 6-cm distance from the sensing plates can be detected by a lightweight algorithm.

This paper presents the design of an integrated current-controlled oscillator (CCO) based readout front-end for neurochemical sensing applications. The readout front-end chip is implemented in 65 nm CMOS technology and occupies an area of 0.059 mm2. The proposed design supports an input current range of 1.2 μA (±600 nA) and can also be configured to support wider current range. The CCO-based structure utilized in this design results in noise averaging of the detected neurochemical input signal due to its inherent ΔΣfirst-order noise shaping and anti-alias filtering characteristics. Thus, the prototype chip achieves a current resolution of 100 pA and can detect dopamine concentrations as small as 10 μMol based on measured data from novel diamond-like carbon electrodes. In addition, the digital codes obtained from the readout front-end attain a signal-to-noise (SNR) of 82 dB and linearity limited effective-number-of-bits (ENOB) of 8 at full current range input, without employing any calibration or linearization techniques. The proposed read-out front-end consumes 33.7 μW of power in continuous operation.

This paper discusses how Differential Pulse Position Modulation (DPPM) can increase the energy efficiency of an UWB impulse radio transmitter when compared to On-Off Keying (OOK). In DPPM, data words are coded in time intervals between consecutive pulses and it saves energy as less pulses are transmitted per bit. A method is shown for minimizing the energy con sumption per bit of a DPPM transmitter by choosing an optimal data word length. Measurement results show an energy efficiency improvement of 45.2%. The jitter of a low-power, low-performance reference clock used in the modulation could cause an unsatisfactory bit error ratio (BER). However, the measurements show that a 1.4 μW, 10 MHz ring oscillator (RO) can enable a BER better than 10-6. The measured transmitter has been implemented in a 180 nm CMOS technology.

In this paper, we present a blackout and brownout insensitive energy harvesting ASIC for ultra-low power autonomous sensor applications. It utilizes both RF or DC power inputs to deliver a regulated voltage for on-chip and off-chip devices. A voltage limiter has been integrated for overvoltage protection. As the ASIC utilizes two regulators alternately, a kick-start method has been used for switching the operation mode. The ASIC is implemented in a 0.18 μm CMOS process. It is able to use a wide range of input DC voltages (0.8...2 V at -40...85 °C) or input AC powers down to -14 dBm.

This paper presents an SPI interface, a mux-based synchronizer and a DSP block designed for a 2-axis accelerometer IC. The SPI interface is used for writing trim bits to the IC and reading acceleration data. Clock output pin is omitted and data can only be read asynchronously. The synchronizer improves the mean time between failures (MTBF) when multi-bit acceleration data is moved from the domain of an on-chip clock to an SPI master device. Estimated MTBF of the synchronizer is 2.2·10468years. The DSP block decimates 1-bit acceleration data coming from two 1-bit ΔΣ AD converters, increases their word lengths and reduces offset and gain errors induced by process variation. The blocks have been implemented in a 0.35 μm CMOS process and their measured dynamic current consumption is 11.8 μA from a 3.3 V supply.

This paper presents a two-regulator power management system for ultra-low power energy harvesting applications. The system consists of an RF-to-DC converter, an LDO and an SC regulator that are connected in parallel operating alternately, and a voltage detector for choosing the operation mode. The system produces a stable 1.2-V output power supply, using a wide range of input DC voltages (0.7...2 V) or input AC powers down to -14 dBm. The system is implemented in a 0.18 μm CMOS process and it has been characterized with load currents from zero to 100 μA.

This paper presents a MEMS-based real time clock with a temperature compensation system. The implemented circuit achieves a timekeeping accuracy of ±4 ppm over -40 °C... 85 °C temperature range. It is built using a 27 kHz silicon resonator, differential PTAT temperature sensor with a 2ndorder ΣΔADC, and a DSP block for temperature frequency compensation. The circuit is powered by a 1.8V supply and draws 2 μA current. The system has been implemented using a 0.18 μm CMOS process.

The attenuation of supply noise is crucial in those sensor interface circuits that require the detection of the small signal capacitance. This paper presents an integrated charge-pump based continuous frequency regulator for precision supply voltage generation. The circuit is able to operate with external supply voltage ranging from 3.0 V to 5.5 V. The charge-pump generates a nominal voltage of 3.6 V and is able to operate with 1.3 mA and 2.5 mA load currents while the minimum input noise attenuation is around 53 dB. The output noise of the system is 91.32 μVrmsand the active area of the circuit is 0.18 mm2. The technology used for the implementation is 0.35 μm CMOS.

This paper presents a ΔΣ ADC designed for a low power microsensor application. Power saving is achieved by utilizing input signal double sampling and a high impedance CM voltage source. In addition to supply voltage and ground, no low impedance references are used. CDS technique is successfully combined with the circuit utilizing the high impedance CM voltage source. The circuit is implemented in 0.35 μm CMOS process using a 3.6 V supply voltage. The 250 kHz clock for the ADC is generated on-chip. The measured results show an input referred noise density of 1.3 μV/√(Hz) and a maximum SNR of 83 dB for a 1 kHz noise BW. Power consumption of the circuit, excluding the clock generator, is 170 μW.

In this paper, simulated and measured phase noise characteristics for a charge-pump phase-locked loop (PLL) with a switched capacitor loop filter are presented. The PLL is fabricated using a 0.35 mum high-voltage CMOS technology. The PLL is designed for a reference frequency range from 3 kHz to 10 kHz, for divider value of 32, and to operate in temperature range from 40degC to +85degC and with 2.5 to 3.6 V supply. Measured results indicate that the SC-filter can be used to replace the conventional RC-filter in order to reduce area.

In this paper we describe how the location and size of an object in a multi-object scene can be identified and classified using a processor array with a scalable region of interest. Objects of interest can be classified by matching them with 25-pixel object prototypes in a window that is adjustable from 17 x 17 to 5 x 5. Matlab simulations of the algorithms are shown. In order to carry out the operations effectively, the processor is equipped with a global OR and global sum. Also, the outputs of the row and column decoders can be determined by boundary cell outputs, in addition to the address bits. A 64 x 64-cell array has been sent to fabrication.

In a 3-axis compass, the system tilt of the sensors needs to be compensated to calculate the heading of the compass correctly. A novel tilt compensation algorithm using the CORDIC algorithm is presented. Only five 2D-CORDIC operations are needed to ac quire the heading angle from three components of magnetic and acceleration data. This can be useful in ASIC and FPGA designs where the compass data needs to be compensated efficiently in terms of area and power. It is also possible to implement the correction algorithm in a micro-controller without a multiplier. The algorithm was tested in practice using a 3-axis magnetometer, a 3-axis accelerometer and FPGA.

A variable block-size analog motion estimation architecture is presented. The advantage of analog motion estimation is that it can be realized in connection with a sensor array. The reference data is stored within the processing array, and thus the memory transfers associated with digital realizations are not required. The architecture is capable of performing motion estimation with all of the seven different block sizes used in state-of-the-art video standards, such as H.264. By using a deep-submicron process, a novel interconnect strategy with 30 connections per cell has been developed. This interconnect strategy enables connecting the various block sizes. Also introduced is a analog motion estimation cell which is more robust against analog inaccuracies than previous implementations. Further, additional computational elements can be added so that the array can determine a block-size partition without the need for an initial search or Lagrange estimation.

This paper describes a ratio-independent algorithmic ADC architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40 kS/s ADC with an active die area of 0.041 mm2is implemented in a 0.13μm CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4μW power dissipation, the ADC achieves 80.2 dB SFDR and 63.3 dB SNDR.

In this paper, a micropower CMOS voltage, current, and temperature reference fabricated in a 0.13μm CMOS process is presented. This bandgap-based circuit provides all reference voltages and currents, and temperature information for a low-power interface of a three-axis capacitive microaccelerometer. The total measured current consumption including all required reference voltage buffers, current mirrors, and scaling circuitry is 23.1μA. The simulated current consumption of the core circuit is 5.5μA. According to system measurements, the required resolutions, 10 bits for the reference voltages and 9 bits for the temperature reference, are achieved. The measured TC for the voltage reference is 9.9ppm/°C, and the analog output of the temperature reference is linear with a 4.9mV/°C slope.

In this paper, measurement results for a micropower 2 MHz CMOS frequency reference circuit fabricated with a 0.13 mum CMOS process are presented. This frequency reference circuit, based on source-coupled CMOS multivibrator, provides the clock signal for a read-out circuit of a capacitive sensor. In addition to low power consumption, good frequency stability is required. Supply independent biasing and symmetrical loads are used to optimize the frequency stability. The typical power consumption is 3.0 muW at room temperature with 1.8 V supply voltage. When properly calibrated, the frequency stays within plusmn2.5% of the nominal oscillation frequency in the operating voltage range of 1.8-2.5 V (with plusmn10% variation) over a temperature range from -35 to +85 degC. The measured phase noise and jitter agree well with the simulations

A channel-select filter for a multicarrier WCDMA receiver targeted for base-station applications is described in this paper. The 4th-order Chebyshev lowpass filter with a 0.1-dB passband ripple is designed to drive high-resolution A/D converters. The -3-dB frequency of the implemented filter is 10 MHz in order to receive two adjacent downconverted WCDMA channels. The filter is designed to have high in- and out-of-band dynamic ranges. It achieves +25-dBV in-band IIP3, +37-dBV out-of-band IIP3, and 11.2-nV/radicHz input-referred noise density. The circuit uses a 2.5-V supply and has been fabricated with a 0.25-mum SiGe BiCMOS process

The design of a high linearity current-mode mixer, which is targeted for base-station (BS) direct-conversion receiver, is described in this paper. Several different configurations based on the Gilbert cell mixer are compared to achieve a high input referred third-order interception point (IIP3) performance with a low noise figure (NF). According to the simulations the designed mixer achieves +15-dBm IIP3 and 10-dB NF. The mixer draws 7 mA from a 2.5-V supply and has been fabricated with a 0.25-mum SiGe BiCMOS process

The MPEG-4 core profile enables object-based coding. A core profile encoder may also have to be able to carry out simple profile frame-based coding. Frame-based coding is, for instance, needed when the object-based functionalities are not used or the target decoder has only simple profile capabilities. cellular nonlinear networks (CNN) offer an effective method to implement the segmentation needed in object-based coding. CNN can be implemented very efficiently with dedicated parallel processor arrays. These parallel processor arrays can integrated with sensor arrays in low-power low bit-rate mobile video encoders. It is shown here that an object-based core profile encoder can have advantages in frame-based simple profile encoding. The intermediate results of a CNN segmentation algorithm can be used in computational complexity reduction of motion estimation (ME). The CNN intermediate results indicate areas of motion within a frame. The areas without motion can be then used to stop the ME or to indicate MPEG-4 skip modes. All block-based ME algorithms can benefit from this knowledge. The intermediate results of the segmentation algorithm are evaluated with the full search and MVFAST ME algorithms. Rate-distortion and computational complexity results are computed with four different reference frame schemes. Considerable improvement in output bits and computational complexity is seen without loss in subjective video quality. The method also has applications in scene change detection.

In this paper, design and implementation of a multicarrier quadrature amplitude modulation (QAM) modulator for a wideband code division multiple access (WCDMA) base-station with a 14-bit on-chip D/A converter is described. The modulator is capable of modulating four carriers with four independent in phase (I) and quadrature (Q) data streams. The proposed modulator structure consists of an interpolation chain for data streams and four digital frequency synthesizer/modulators, which are based on a coordinate rotation digital computer (CORDIC) vector rotation algorithm. The interpolation chain consists of a root-raised cosine pulse shaping filter and three half-band filters for image filtering. The modulated carriers are combined to form a multicarrier WCDMA signal. The SINC-attenuation effect of a digital/analog (D/A) converter is canceled by an inverse-SINC predistortion filter. The multicarrier signal is converted to the analog domain with a 14-bit current steering D/A converter, which is integrated on the same silicon chip. The modulator is implemented with a 0.35-mum BiCMOS process with CMOS transistors only

In this paper a design method for building high speed array computers on a single chip is demonstrated with two example realizations. The key idea in the method is that an array computer can be built using reusable, relatively simple building blocks. All necessary memory is distributed among processing units. The number of processing units in the array computer is selected based on speed requirements, yielding a low power, small die area realization. Two different measured array processor realizations designed using the method are depicted.

In this paper realization of couplings between cells in a polynomial type mixed-mode cellular neural network (CNN) is analyzed. The choice of the multiplier is discussed and two multiplier types are analyzed. Also, two circuits for generating the second and third order polynomial terms of cell output are described. The accuracy of the multipliers and polynomial circuits at the presence of device mismatch is analyzed.

In conventional base station solutions, the carriers transmitted are combined after the power amplifiers. An alternative to this is to combine the carriers in the digital domain. The major drawback of the digital carrier combining is a strongly varying envelope of the composite signal. The high PAR, sets strict requirements for the linearity of the power amplifier. High linearity requirements for the power amplifier leads to low power efficiency and therefore to high power consumption. In this paper, the possibility of reducing the PAR by clipping is investigated in two cases, GSM and EDGE.

A multicarrier Gaussian minimum shift keying (GMSK) modulator has been developed and implemented. The design contains four GMSK modulators, which generate GMSK modulated carriers at the specified center frequencies. Utilization of the redundancy in the stored waveforms reduces the size of the GMSK trajectory look-up table to less than one-quarter of the original size in the modulator. Conventionally, the power ramping and output power level controlling are performed in the analog domain. A novel digital ramp generator and output power level controller perform both the burst ramping and the dynamic power control in the digital domain. The power control is realized by scaling the ramp curve, which follows a raised cosine/sine curve. The four GMSK modulated signals are combined together in the digital domain. The digital multicarrier GMSK modulator is designed to fulfil the spectrum and phase error specifications of the GSM 900 and DCS 1800 base stations.

A multicarrier QAM modulator for the wideband code division multiple access (WCDMA) basestation has been designed. The multicarrier modulator performs pulse shaping filtering for four baseband I and Q data streams. The filtered data is interpolated in three stages each interpolating with a factor of two. The modulation of four independent carriers is performed with the numerically controlled oscillators (NCO) which are based on the CORDIC vector rotation algorithm. The multi-carrier output is formed by summation of the modulated carriers. The SINC-attenuation effect of the D/A-converter is canceled by an inverse-SINC predistortion filter. The goal of the design process was to make the performance of the modulator limited by the 14-bit D/A-converter which can be considered as the state of the art available at IF frequencies.

In this paper the design issues of large globally connected compact neural networks are targeted. Building blocks of a cell that is capable of performing the hardware annealing function are designed. Different offset compensation schemes are used to eliminate the offset currents. The cell is designed to have voltage outputs to facilitate the interconnecting of cells. The blocks are processed with a 0.5 /spl mu/m standard digital CMOS process and measurement results of selected building blocks of the cell are included.

The implementation of the internal A/D-converter in a /spl Delta//spl Sigma/-modulator can be simplified by utilizing two-step quantization, which makes the internal quantization feasible with much higher resolution than with conventional solutions. The A/D-conversion is divided into two time steps which significantly reduces the circuit complexity when compared to flash type conversion. The loop stability is sustained by feeding back a coarse result obtained during the first time step. The second step yielding a finer resolution is interleaved with the next sample so that the resolution improvement is achieved without sacrificing the speed. It is shown, with a linearized model, that the order of the noise shaping is increased by one with respect to the coarse quantization error made during the first step. For a high oversampling ratio the coarse quantization error made in the first step is easily suppressed to an insignificant level due to the one order higher noise shaping. Depending on the partitioning of the bits between the conversion steps the coarse error will dominate below a certain oversampling ratio. However, it is shown that the technique can be extended to more than one order higher noise shaping making it usefull for low oversampling ratios as well.

In this paper the effect of the number of parallel channels and the stage resolution on the sample rate and power dissipation of time interleaved parallel pipeline analog-to-digital converters (ADC's) with identical stages are examined. Simple formulas are given to determine an optimum number of parallel channels and stage resolution for a given technology with respect to the conversion rate and current consumption. The formulas are applied for to 10 bit pipeline ADC using a standard 0.5 /spl mu/m CMOS process parameters.

The design and performance of a rail-to-rail low-voltage CMOS fifth-order elliptic low-pass GM-C filter for baseband mobile communication are presented. The operational transconductance amplifier (OTA) used in this filter is a low-voltage rail-to-rail voltage-to-current converter (V-I converter). In this V-I converter, an N-type V-I converter cell is connected in parallel with its counterpart, a P-type V-I converter cell, to achieve common-mode (CM) rail-to-rail operation. Two maximum-current selecting circuits and an output current subtraction circuit are utilized to generate constant-g/sub m/ output currents for this OTA. This fifth-order elliptic low-pass GM-C filter operates at a supply voltage of 3 V and has a cutoff frequency of 280 to 405 kHz. It provides up to 700 mV/sub pp/ output with 1% total harmonic distortion (THD), dissipates 2.48 mW at V/sub cm/=1.5 V, and occupies 1.62 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.

A fast fully-differential 6th order switched-current ladder filter with transmission zeros has been designed with a 1.2 um CMOS-process. The low-pass cut-off frequency of the filter is 630 kHz and it has a transmission zero at 950 kHz. The used clock frequency is 10 MHz. The filter is constructed with a novel fully-differential SI-integrator. The chip includes the voltage-to-current and the output current-to-voltage converters. The performance-of the SI-filter is compared with the equivalent SC-realization.>

Integrated IF-modules for mobile phone applications have been designed with-1.2 um BiCMOS technology. These modules consist of the transmitter, receiver and temperature independent gain-adjustment circuits. The 80 dB dynamic range over 50 MHz bandwidth of both the transmitter and receiver is achieved with the current stearing gain control amplifier. The gain control amplifier has an 80 dB dynamic range which is achieved with the current stearing gain control amplifier. The gain control is linear within +/- 0.5 dB and temperature compensated. The temperature compensation is performed in current mode. The dynamic range requirement is especially challenging for the logarithmic amplifier in the peak detector, in which a current feedback amplifier has been applied. These modules are intended to be combined on a single chip with the realised baseband filtering circuit. The total area of the circuits is 6 mm2 and the power consumption is 60 mA.>

The designed BiCMOS current-feedback operational amplifier utilizes a novel circuit topology which enables constant 1 MHz bandwidth closed loop voltage gains up to 60 dB. The offset current of the current-feedback amplifier is canceled with an active OTA-C feedback loop. The amplifier is fabricated with a 1.2 micron BiCMOS-process (NPN f/sub T/ 7 GHz).>

A new way of implementing a cellular neural network cell using simple differential stages is described. Also some aspects for implementing associative memory with this new structure are discussed.>

In this paper the control voltage related temperature dependencies of a current deviation based AGC amplifier are studied. A control circuit with linear and temperature compensating gain control is presented.>