Timing-driven global placement plays a decisive role in the final performance of very large-scale integration (VLSI) circuits, but is consistently challenged by the trade-off between design accuracy and efficiency. Most existing methods rely on coarse-grained net-weighting strategies. While these approaches are straightforward to implement, they cannot precisely identify and optimize complex timing paths, such as paths with sharing effects or large slack deviations. To overcome this bottleneck, we propose a high-precision slack-aware global placement engine called HPPlacer, which includes the following three key techniques: 1) a local clock buffer-to-flip-flop connection optimization method, 2) a path-level differentiable timing optimization model, and 3) a dynamic adjustment mechanism-based pin-pair weighting strategy. With the proposed method, efficient chip placement with excellent timing behaviors can be generated automatically within a short period of time. The experimental results on multiple benchmark circuits confirm that HPPlacer leads to significant improvements in both timing performance and wirelength compared to state-of-the-art placement tools.

With the widespread application of distributed supply chains in the field of microfluidic biochips, significant improvements have been made in the design, manufacturing, and application efficiency of biochips. However, this model also introduces new security risks, as malicious attackers could tamper with biochemical protocols at any stage of the supply chain, leading to experimental failures. To this end, we propose an automated anomaly detection method for biochemical protocols in continuous-flow microfluidic biochips for the first time. On one hand, we propose a preprocessing method for watermark embedding in biochemical protocols, which performs abstract modeling of biochemical protocols to calculate the variable bit range of protocol parameters, thereby providing necessary preprocessing support for subsequent watermark embedding. On the other hand, we propose an optimization method for watermark embedding in biochemical protocols, which integrates the design of a weighted loss function based on attribute importance with the selection of watermark embedding positions based on simulated annealing to determine the optimal embedding position, thereby ensuring the robustness of watermark embedding. Experimental results on multiple benchmarks indicate that the proposed method can efficiently realize the abnormal detection of biochemical protocols and has high detection probability and strong robustness.

Continuous-flow microfluidic biochips (CFMBs) are advanced platforms that precisely manipulate fluids through micron-scale channels and have been widely applied in biomedical research and disease diagnostics. Their internal architecture typically employs multiplexer-based control logic, where control channels transmit input signals to flow valves to dynamically switch fluid paths and achieve precise control. However, the reuse and elimination operations of control channels introduce a large number of L-shaped structures. These structures are prone to channel deformation and, under high-frequency usage, can accelerate structural fatigue, thereby reducing the reliability of the control logic. In addition, improper control channel reuse may lead to signal conflicts and interference. To address these problems, we propose a control logic architecture design approach for CFMBs that simultaneously considers channel length and straightness. First, we propose a placement preprocessing strategy that integrates a heuristic initialization with a critical-path-first approach to improve the quality of the initial placement and ensure feasibility. Second, we design a placement algorithm based on discrete particle swarm optimization with a twin-swarm cooperative mechanism, which effectively explores better placement solutions through cooperative search between the two swarms and feedback from routing results. Finally, we propose a two-stage routing algorithm that integrates error recovery and reuse constraints. By incorporating straightened routing and reasonable reuse, this algorithm significantly reduces channel length and the number of bends while ensuring the correctness of the control logic. Experimental results demonstrate that the proposed approach enables reliable control of flow valves with fewer resources and effectively reduces signal propagation delay in control channels, significantly enhancing the overall performance and reliability of the control logic.

Rapid advances in microfluidics technologies have facilitated the emergence of highly integrated lab-on-a-chip (LoC) biochip systems. With such a coin-sized biochip, complicated bioassay procedures can be executed efficiently without any human intervention. To ensure the correctness of assay outcomes, however, cross-contamination among different fluid samples and reagents needs to be dealt with separately during assay execution. As a consequence, washing operations have to be introduced and a washing path network needs to be established on the chip to remove the residues left behind in flow channels/devices. Also, chip drying after washing operations is crucial for maintaining some properties (e.g., pH values) of the subsequent reagents, so that precision degradation caused by residual buffer fluids can be avoided for those concentration-sensitive assays. To realize optimized assay procedures, we consider both washing operations and chip drying for the first time and propose an integer linear programming (ILP)-based path-driven washing and drying cooptimization method called PathDriver-WD for continuous-flow LoC biochip systems. The proposed method includes the following four key techniques: 1) The necessity of contamination removals and channel drying is analyzed systemically to avoid unnecessary washing and drying operations, 2) washing and drying operations are integrated with the regular removal of excess fluids, so that extra channel occupation can be minimized, 3) practical computation models are adopted to evaluate the durations of different washing and drying operations, and 4) optimized washing/drying paths and time windows are computed and assigned so that the completion time of assays can be minimized. Simulation results on multiple benchmarks demonstrate that the proposed method leads to highly efficient washing and drying procedures as well as minimized assay completion time.

With the increasing integration level of flow-based microfluidics, fully programmable valve arrays (FPVAs) have emerged as the next generation of flow-based microfluidic devices. Microvalves in an FPVA are typically managed by a control logic, where valves are connected to a core input via control channels to receive control signals that guide their state switchings. When executing bioassays using an FPVA, however, some valves need to be switched synchronously at different time points, so that both fluid transportation and biochemical operations can be executed correctly. Consequently, the channel lengths from the core input to these valves must be equal, which poses a big challenge to the channel routing of the control logic. To solve this problem, we propose a deep reinforcement learning-based adaptive routing flow for the control logic of FPVAs. With the proposed routing flow, an efficient control-channel network can be automatically constructed to realize accurate control signal propagation. Meanwhile, timing skews among synchronized valves and the total length of control channels are minimized simultaneously, thus generating an optimized control logic with excellent timing performance. Furthermore, by introducing backups of identified critical valves and flexible routing of backup paths without restrictions on control valve locations, a novel fault-tolerant design method considering length matching is implemented to efficiently improve the reliability of the control logic. Simulation results on multiple benchmarks demonstrate that the proposed routing flow leads to control logics with accurate valve synchronization, low cost, and high reliability.

Flow-based microfluidic biochips have attracted much attention over the past two decades. By integrating diverse micro-components, e.g., mixers and filters, on a miniaturized planar substrate, complicated bioassays such as protein crystallization and drug screening can be executed automatically without requiring human invention, thus becoming a promising alternative to traditional cumbersome laboratory equipment. As manufacturing technology advances, it has become possible to implement hundreds of thousands of microvalves within a single chip. This breakthrough has given rise to fully programmable valve array (FPVA) biochips, representing a next-generation platform in flow-based microfluidics that offers enhanced reconfigurability and operational flexibility. Nevertheless, the exponential increase in valve density has introduced significant design complexity when implementing sophisticated assay protocols. As a result, the design automation of FPVAs has emerged as a critical research frontier, attracting considerable attention from both academia and industry. This review article systematically examines recent advances in FPVA design automation, involving computer-aided design methods for architectural synthesis, volume management, sample preparation, automated testing, fault localization, error recovery, and washing optimization. These techniques enable FPVA users to concentrate on assay protocol development while delegating implementation-specific design and optimization tasks to design automation tools. Furthermore, we analyze emerging security implications in FPVAs, particularly focusing on bioassay accuracy and reliability that ensure experimental reproducibility. Finally, potential trajectories for future research are discussed in detail to further promote the integration level and widespread application of FPVAs.

The track assignment has been introduced between global routing and detail routing. Based on the independence and divisibility of track assignment, we propose a GPU-accelerated parallel track assignment algorithm. To estimate routability more accurately, the proposed algorithm simultaneously considers global and local nets, and incorporates several strategies for optimization. Moreover, an asynchronous parallelism strategy is proposed to divide the computation of routing resources and the track assignment into fine-grained tasks. Experimental results show that, compared to related work, our algorithm achieves a significant speedup with a better routability estimation.

The Steiner minimum tree (SMT) serves as an optimal connection model for multiterminal nets in very large scale integration (VLSI). Constructing both rectilinear SMT (RSMT) and octilinear SMT (OSMT) are known to be NP-hard problems. Simultaneously, constructing multiple topologies of SMTs for a given net holds significant importance in alleviating routing constraints such as alleviating congestion and ensuring timing convergence. However, existing efforts predominantly focus on designing specialized methods to construct a specifically structured SMT for a given net, making it challenging to extend to different structures or topologies of SMTs, while also exhibiting insufficient optimization capabilities. In this work, we propose a unified approach based on deep reinforcement learning (DRL) to address both RSMT and OSMT problems while generating diverse routing topologies. First, we design an edge point sequence (EPS) that leverages the structural characteristics of SMT to connect the output of the deep learning model with the SMT structure. Second, we propose a deep learning model tailored for EPS, employing the negative wirelength of SMT as a reward to train the model using DRL. Third, we provide a corresponding rapid and accurate wirelength computation algorithm for evaluating the quality of the construction solution to expedite model training. Finally, we leverage the stochastic nature of machine learning to construct diverse SMT construction solutions. To the best of our knowledge, this is the first unified approach capable of simultaneously addressing both RSMT and OSMT problems while generating diverse solutions. The proposed unified approach demonstrates superior solution quality and higher efficiency compared to specifically designed algorithms.

As a new generation of flow-based microfluidics, Fully Programmable Valve Array (FPVA) biochips have gained widespread adoption as a biochemical experimental platform, thanks to their enhanced programmability and flexibility. Environmental and human factors, however, often introduce physical faults during the manufacturing process such as channel blockage and leakage, which, undoubtedly, can affect the results of bioassays and even cause execution failure. In this paper, we focus on the fault-tolerant co-design of flow and control layers in FPVA biochips for the first time. For the flow layer, three dynamic fault-tolerant techniques, i.e., a cell function conversion method, a bidirectional redundancy scheme, and a fault mapping method, are presented and integrated into the device placement and flow routing stages. As a consequence, we further realize an efficient and effective fault-tolerance-oriented physical design method, thus ensuring the robustness of chip architecture and correctness of assay outcomes. For the control layer, we design another three fault-tolerant techniques including a series duplication scheme of leakage valves, allocation and merging rules of backup valves, and a logic conflict-aware adjustment strategy of redundant architecture. Based on these techniques, we construct a fault-tolerant control system to realize dynamic recovery of control signals. Experimental results on multiple test cases demonstrate that the proposed method can produce optimized fault-tolerant FPVA architectures with low fabrication cost, high execution efficiency, and high fault-tolerance success rate.

Routability has always been a significant challenge in Very Large Scale Integration (VLSI) design. To overcome the potential mismatch between the global routing results and the detailed routing requirements, track assignment is introduced to achieve an efficient routability estimation. Moreover, with the increasing scale of circuits, the intricate interconnections among the components on the chip lead to increased timing delay in signal transmission, thereby significantly impacting the performance and reliability of the circuit. Thus, to further improve the routability of the circuit, it is also critical to realize an accurate estimation of the timing delay within the track assignment stage. Existing heuristic track assignment algorithms, however, are prone to local optimality, and thus fail to provide accurate routability estimations. In this article, we propose an enhanced scalable parallel track assignment algorithm called SPTA 2.0 for VLSI design, employing a two-stage partition strategy and considering timing delay. First, the proposed algorithm achieves efficient assignment of all wires by considering the routing information from both the global and local nets. Second, the overlap cost, the blockage cost, and the wirelength cost can be minimized to significantly improve the routability. Third, a critical wire controlling strategy is proposed to optimize signal timing delays inside nets. Finally, a two-stage partition strategy and a panel-subpanel-level parallelism are designed to further reduce the runtime, improving the scalability of the proposed methodology. Experimental results on multiple benchmarks demonstrate that the proposed method provides better routability estimations, and leads to superior track assignment solutions compared with existing algorithms.

With the increasing integration level of flow-based microfluidics, fully programmable valve arrays (FPVAs) have emerged as the next generation of microfluidic devices. Mi-crovalves in an FPVA are typically managed by a control logic, where valves are connected to a core input via control channels to receive control signals that guide states switching. The critical valves that suffer from asynchronous actuation leading to chip malfunctions, however, need to be switched simultaneously in a specific bioassay. As a result, the channel lengths from the core input to these valves are required to be equal or similar, which poses a challenge to the channel routing of the control logic. To solve this problem, we propose a deep reinforcement learning-based adaptive routing flow for the control logic of FPVAs. With the proposed routing flow, an efficient control channel network can be automatically constructed to realize accurate control signals propagation. Meanwhile, the timing skews among synchronized valves and the total length of control channels can be minimized, thus generating an optimized control logic with excellent timing behavior. Simulation results on multiple benchmarks demonstrate the effectiveness of the proposed routing flow.

Fully Programmable Valve Array (FPVA) biochips have attracted much attention as a new generation of continuous-flow microfluidic platform for biochemical experiments automation. With the increasing density of microvalves in FPVA biochips, the control system for managing the open/close of these valves has become more and more complex. To improve the scalability of biochips and reduce the number of control pins, a highly efficient control system using multiplexer and boolean logic has been introduced in FPVA biochips. In the manufacturing and using of such systems, however, various faults such as channel blockage, channel leakage, and reliability issues caused by frequent valve switching can occur in the multiplexers. Accordingly, in this paper, we propose the first automated fault test method for the multiplexer of FPVA control systems. The proposed method includes the following key techniques: 1) an automated test pattern generation algorithm based on integer linear programming and 2) an automated fault test strategy based on image recognition technology. Experiment results on multiple benchmarks have shown that the proposed method can generate fewer test patterns, while achiving 100% fault coverage.

Rapid advances in microfluidics technologies have facilitated the emergence of highly integrated lab-on-a-chip (LoC) biochip systems. With such coin-sized biochips, complicated bioassay procedures can be executed efficiently without any human intervention. To ensure the correctness and precision of assay outcomes, however, cross-contamination among different fluid samples/reagents needs to be dealt with separately during assay execution. As a consequence, wash operations have to be introduced and a wash path network needs to be established on the chip to remove the residues left in flow channels. To realize optimized assay procedures with efficient wash operations, we propose PathDriver-Wash in this paper, a path-driven wash optimization method for continuous-flow LoC biochip systems. The proposed method includes the following three key techniques: 1) The necessity of contamination removals is analyzed systemically to avoid unnecessary wash operations, 2) wash operations are integrated with the regular removal of excess fluids, so that extra path occupations caused by wash can be minimized, and 3) optimized wash paths and time windows are computed and assigned to wash operations, so that the completion time of assays can be minimized. Experimental results demonstrate that the proposed method leads to highly efficient wash procedures as well as minimized assay completion times.

In recent years, Fully Programmable Valve Array (FPVA) has emerged as a promising alternative for microfluidic biochips with flexible features. When two fluids flow sequentially through the same microchannel, the latter will be contaminated by the former’s residues. To solve the contamination problem, the buffer should be injected into microchannel to wash the contaminated area before reusing the microchannel. Considering the buffer capacity limitation, this paper proposes a washing optimization method based on Deep Reinforcement Learning (DRL), which aims to minimize the washing time and buffer washing capacity. First, a preprocessing method for the washing optimization problem is designed to generate the inputs for the initial state of the DRL environment based on the given physical design scheme. Second, an FPVA biochip simulation environment is constructed. In addition, the corresponding state, action space and high-precision reward function are designed. Finally, a new washing optimization framework is formulated based on DRL, which adopts the Proximal Policy Optimization (PPO) algorithm and Convolutional Neural Networks (CNN) to implement the washing decision. Experimental results on several benchmarks show that the proposed washing optimization method can further reduce the washing time and buffer washing capacity in comparison with related work.

Due to manufacturing defects, chip aging, and potential malicious attacks, unexpected errors may occur in the valves of Fully Programmable Valve Array (FPVA) biochips. To address this issue, an error recovery method based on Deep Reinforcement Learning (DRL) for FPVA biochips to handle valve-related unexpected errors is proposed, which involves designing specific error recovery operations for different error types, introducing a sequencing graph adjustment method to generate error recovery sequencing graph, and designing a resynthesis method to realize error recovery. The resynthesis method contains a priority-based scheduling adjustment, a DRL-based placement adjustment, and a DRL-based routing adjustment, which aims at updating the execution timetable for operations, component placements, and fluid transport paths. The model parameters are updated using a proximal policy optimization algorithm, continually learning from a large number of randomly simulated error scenarios, resulting in strong generalization performance. In comparison to existing work, the proposed method achieves lower probability of error recovery failure, shorter completion time of bioassay, and faster runtime.

Continuous-Flow Microfluidic Biochips (CFMBs) have been widely applied in various biochemical fields due to their capabilities of precise control, high integration, and automation. However, insecure supply chains enable malicious actors to tamper with biochips, compromising their integrity and leading to failed bioassays. Additionally, the limited availability of detection resources leads to increased costs and reduced efficiency in conducting bioassays. To ensure accurate and efficient execution of bioassays, this paper defines fluid scheduling tampering and activation sequences tampering as two types of security threats and proposes an Anomaly Detection method based on Discrete Particle Swarm Optimization (AD-DPSO) for CFMBs. The AD-DPSO method presents a weight calculation strategy based on fluid scheduling and a checkpoint selection strategy based on DPSO to effectively deploy checkpoints on the biochips. The weight calculation strategy ensures effective and secure checkpoint deployment strategies by favoring units with high usage frequency and low detection cost. The checkpoint selection strategy comprehensively considers chip resources and security requirements, thus maximizing the probability of anomaly detection while minimizing associated costs. Compared to the existing work, the proposed AD-DPSO achieves higher Return on Investment and lower detection costs with high detection probability.

Fully programmable valve array (FPVA) biochips have emerged as a promising alternative for traditional application-specific microfluidic platforms thanks to their advantages in terms of flexibility and reconfigurability. By regularly deploying microvalves along vertical and horizontal flow channels, microfluidic modules with different sizes and shapes can be constructed dynamically on the chip, thereby enabling the automatic execution of various assay procedures in biology and biochemistry. The above advantages, however, result largely from the large-scale integration of valves as well as accurate control of their switchings, leading to very complicated control-logic design of such chips. In this article, we propose an reinforcement learning (RL)-based synthesis flow for the control-logic design of fully programmable valve array (FPVA) biochips, taking multichannel switching and control-cost minimization into consideration simultaneously. By employing a double deep$Q$-network (DDQN) and two Boolean-logic simplification techniques, control logics with both high-switching efficiency and low-fabrication cost can be constructed automatically. Furthermore, the solution space of multichannel-switching combinations is reduced to improve the search efficiency of the proposed method. Experimental results on multiple benchmarks demonstrate that the proposed synthesis flow leads to better-design solutions compared with the state-of-the-art techniques.

With the advances in microfluidics, electrowettingon-dielectric (EWOD) chips have widely been applied to various biological and chemical laboratory protocols. Glass-based EWOD chips with non-regular electrodes are proposed, which allow more reliable droplet operations and facilitate the integration of optical sensors for many biochemical applications. Furthermore, non-regular electrode designs are utilized in EWOD chips, e.g., interdigitated electrodes for more reliable droplet manipulation, custom shaped electrodes for specific applications like concentric heating, etc. However, due to the technical challenges of fabricating multi-layer interconnection on the glass substrate, e.g., unreliable process and high cost, both control electrodes and wires are fabricated with a single-layer configuration, which poses significant challenges to pin selection for non-regular electrodes. In this paper, we propose a minimum-cost flow-based routing algorithm called NR-Router+ that features efficient and robust routing for single-layer EWOD chips with non-regular electrodes. To the best of our knowledge, this is the first work that overcomes the aforementioned challenges. We construct a minimum-cost flow algorithm to generate optimal routing paths followed by a light-weight model to handle flow capacity. A grid reduction strategy is proposed to reduce the computational overhead. Additionally, a flow collocation algorithm based on integer linear programming is presented to efficiently prevent wire overlapping. Experimental results show that NR-Router+ achieves 100% routability while minimizing wirelength with shorter run time. Moreover, NR-Router+ can generate mask files feasible for manufacturing via adjustments of design parameters, thus demonstrating its robustness and efficiency.

Continuous-flow microfluidic biochips are gaining increasing attention with promising applications for automatically executing various laboratory procedures in biology and biochemistry. Biochips with distributed channel-storage architectures enable each channel to switch between the roles of transportation and storage. Consequently, fluid transportation, caching, and fetch can occur concurrently through different flow paths. When two dissimilar types of fluidic flows occur through the same channels in a time-interleaved manner, it may cause contamination to the latter as some residues of the former flow may be stuck at the channel wall during transportation. To remove the residues, wash operations are introduced as an essential step to avoid incorrect assay outcomes. However, existing work has been considered that the washing capacity of a buffer fluid is unlimited. In the actual scenario, a fixed-volume buffer fluid irrefutably possesses a limited washing capacity, which can be successively consumed while washing away residues from the channels. Hence, capacity-aware wash scheme is a basic requirement to fulfil the dynamic fluid scheduling and channel storage. In this paper, we formulate a practical wash optimization problem for microfluidic biochips, which considers the requirements of dynamic fluid scheduling, channel storage, as well as washing capacity constraints of buffer fluids simultaneously, and present an efficient design flow to solve this problem systematically. Given the high-level synthesis result of a biochemical application and the corresponding component placement solution, our goal is to complete a contamination-aware flow-path planning with short flow-channel length. Meanwhile, the biochemical application can be executed efficiently and correctly with an optimized capacity-aware wash scheme. Experimental results show that compared to a state-of-the-art washing method, the proposed method achieves an average reduction of 26.1%, 43.1%, and 34.1% across all the benchmarks with respect to the total channel length, total wash time, and execution time of bioassays, respectively.

Global routing is an extremely important stage of very large scale integration (VLSI) physical design. With the rise of nano-scale integrated circuit design, the multilayer global routing problem has attracted considerable research interest during the past few years. In this article, a multilayer X-architecture global routing (ML-XGR) system based on particle swarm optimization (PSO), called FZU-Router, is proposed to solve the ML-XGR problem for the first time. FZU-Router contains a multilayer X-architecture integer linear programming (MX-ILP) model and a multilayer X-architecture PSO (MX-PSO) algorithm, which are presented to formulate and solve the ML-XGR problem, respectively. Moreover, four effective strategies are designed to enhance the efficiency of FZU-Router: 1) a strategy for generating new routing modes is proposed to strengthen the robustness of encoding strategy of MX-PSO; 2) a strategy for combining MX-PSO with maze routing is proposed to improve the routability; 3) a strategy for reducing the channel capacity is proposed to make better use of optimization ability of MX-PSO; and 4) a strategy for dynamic resource assignment is proposed to make better use of routing resources and shorten the running time. Experimental results on multiple benchmarks confirm that the proposed FZU-Router leads to fewer total overflow and shorter total wirelength compared with the state-of-the-art routers.

SMT is an optimized model for solving the routing problem of a multipin net in very large-scale integrated circuits. As the appearance of various obstacles on chips, the obstacle-avoiding problem has attracted much attention in recent years. Meanwhile, since interconnect delay plays a major role in chip delay, timing analysis is another critical problem worthy of consideration when constructing an Steiner minimum tree (SMT). Furthermore, the introduction of theX-architecture allows for better utilization of routing resources. In this article, a timing-driven obstacle-avoiding X-architecture Steiner minimum tree algorithm with slack constraints (TD-OAXSMT-SC) is proposed to consider obstacle-avoiding, timing slack constraints, andX-architecture simultaneously for the first time. The TD-OAXSMT-SC algorithm consists of four major stages: 1) in the routing tree initialization stage, this article constructs anX-architecture Prim–Dijkstra spanning tree as the initial routing tree with minimum total delay; 2) in the particle swarm optimization (PSO)-based routing tree iteration stage, a novel discrete PSO algorithm based on genetic operators is proposed to obtain a high-quality routing tree; 3) in the routing tree standardization stage, two effective standardization strategies are proposed to obtain a routing tree that satisfies both obstacle-avoiding and timing slack constraints; and 4) in the routing tree optimization stage, the connection of interconnected wires is optimized in a global manner, thus obtaining an optimized routing tree. Experimental results show that the proposed TD-OAXSMT-SC algorithm outperforms the state-of-the-art methods in routing quality with slack constraints.

As a new generation of flow-based microfluidics, the Fully Programmable Valve Array (FPVA) biochips have become a popular biochemical experimental platform that provide higher flexibility and programmability. Due to environmental and human factors, however, there are usually some physical faults in the manufacturing process such as channel blockage and leakage, which, undoubtedly, can affect the results of bioassays and even cause execution failure. Accordingly, we focus on the fault-tolerant design of FPVA biochips for the first time in this paper, and present three dynamic fault-tolerant techniques including a cell function conversion method, a bidirectional redundancy scheme, and a fault mapping method. By integrating these techniques into the component placement and channel routing stages, we further realize an efficient and effective fault-tolerance-oriented physical design approach for FPVA biochips, thus ensuring the robustness of chip architecture and correctness of assay outcomes. Experimental results on multiple benchmarks confirm that the proposed approach can generate fault-tolerant FPVA architectures with both high execution efficiency and low fabrication cost.

Owing to the high complexity of chip architecture and assay protocol, considerable effort has been directed toward the design automation of continuous-flow microfluidics over the past decade. Existing methods, however, perform the corresponding design tasks, including binding, scheduling, placement, and routing separately, leading to serious gaps between different steps and potentially even cause design failure. To overcome these drawbacks, in this article, we propose a one-pass design paradigm for continuous-flow microfluidic lab-on-a-chip systems, integrating all the design steps into an “organic whole,” which has never been considered in prior work. With the proposed paradigm, all the design tasks can be synchronized seamlessly and performed in a combined manner, thereby eliminating the gaps between design steps. Consequently, optimized biochip architectures can be generated without any design adjustments and modifications. The experimental results demonstrate the effectiveness of the proposed automation flows.

Digital microfluidic biochips have emerged as a promising alternative for various laboratory procedures in biochemistry, such as drug discovery and DNA sequencing. A recent generation of digital biochips uses a micro-electrode-dot-array (MEDA) architecture, which provides finer controllability of droplets and seamlessly integrates microelectronics and microfluidics. To simplify the wiring design of such biochips, all microelectrodes and their control registers are daisy-chained together. Therefore, the ability to both identify faults in the chain and tolerate them is required in MEDA biochips. In this study, a new daisy-chain design approach is proposed, integrating a built-in self-repair scheme that can automatically detect faults and correct them. Moreover, an efficient test generation method that requires only a small number of test vectors is proposed to achieve 100% fault coverage without degrading the electrodes. The proposed self-repair scheme can be used in both offline and online modes. Experimental results show that detection and repair can be carried out for various types of faults that can occur in daisy chains.

Continuous-flow microfluidic biochips have emerged as a potential low-cost and fast-responsive lab-on-chip platform. They have attracted much attention due to their capability of performing various biochemical applications concurrently and automatically within a coin-sized chip area. To improve execution efficiency and reduce fabrication cost, a distributed channel-storage architecture can be implemented in which the same channels can be switched between the roles of transportation and storage. Accordingly, fluid transportation, caching, and fetch can be performed simultaneously through different flow paths. Such a flow-path planning needs to be considered carefully in the mapping procedure from a biochemical application to a given biochip architecture. Moreover, all the on-chip valves should be actuated correctly and promptly to temporally block the fluid transportation in unwanted directions and seal the fluids in caching channels. Such an exact control of the valves needs to be considered systematically in control-system design to support the mapping scheme for bioassay execution. In this article, we formulate the practical mapping-control co-design problem for microfluidic biochips with distributed channel storage, considering application mapping, valve synchronization, and control-system design simultaneously, and present an efficient synthesis flow to solve this problem systematically. Given the protocol of a biochemical application and the corresponding chip layout in the flow layer, our goal is to map the biochemical application onto the chip with short execution time. Meanwhile, a practical control system considering the real valve-switching requirements can be constructed efficiently with low fabrication cost. Experimental results on multiple real-life bioassays and synthetic benchmarks demonstrate the effectiveness of the proposed design flow.

With the advances in microfluidics, electrowetting-on-dielectric (EWOD) chips have widely been applied to various laboratory procedures. Glass-based EWOD chips with non-regular electrodes are proposed, which allow more reliable droplet operations and facilitating integration of optical sensors for many biochemical applications. Besides, non-regular electrode designs (e.g., interdigitated electrodes) are utilized in EWOD chips to precisely control droplet volume, and electrodes with a specific shape become necessary for certain applications. However, due to the technical barriers of fabricating multi-layer interconnection on the glass substrate (e.g., unreliable process and high cost), both control electrodes and wires are fabri-cated with a single-layer configuration, which poses significant challenges to pin selection for non-regular electrodes under the limited routing resource. In this paper, we propose a minimum cost flow-based routing algorithm called NR-Router that features efficient and robust routing for single-layer EWOD chips with non-regular electrodes, which overcomes the challenges mentioned above. NR- Router is the first algorithm that can accurately route in single-layer EWOD chips with non-regular electrodes to the best of our knowledge. We construct a minimum cost flow algorithm to generate optimal routing paths followed by a light-weight model to handle flow capacity. NR-Router achieves 100% routability while minimizing wirelength at shorter run time, and generates mask files feasible for manufacturing via adjustments of design parameters. Experimental results demonstrate the robustness and efficiency of our proposed algorithm.

Timing optimization has always been a key issue affecting the chip performance. Most of the previous layer assignment algorithms mainly optimize timing from the perspective of interconnect delay, and often ignore the impact of slew on signal integrity. Therefore, this paper proposes LA-SVR, a high-performance layer assignment algorithm with slew violations reduction. The proposed algorithm mainly includes three key techniques: 1) an effective classified reassignment strategy is proposed to re-assign nets in terms of different optimization priorities for overflow avoidance; 2) an effective net adjustment method is adopted to reduce the potential slew violations; 3) a layer restricting strategy is proposed to optimize delay of nets and slew violations simultaneously by restricting the candidate better routing layers of different nets. Experimental results show that the proposed algorithm has a significant effect on slew violations reduction.

Routability has always been a very challenging issue in Very Large Scale Integrated (VLSI) circuit design. The routability is considered in track assignment so that the global routing results can better match the requirements of detailed routing. However, existing heuristic track assignment algorithms are prone to local optimality, which cannot provide the accurate routability estimation. To overcome this limitation, we propose a scalable parallel Integer Linear Programming (ILP)-based track assignment algorithm, called SPTA, which employs a two-stage partition strategy. First, by taking into account both the global and local nets, all wires are assigned to tracks, making full use of the information from the global routing results. Second, an efficient ILP model for track assignment is proposed to minimize the overlap between iroutes1, thus significantly improving routability. Third, a two-stage partition strategy is designed to reduce the runtime. Finally, a panel-subpanel-level parallelism is proposed to further speed up the algorithm without sacrificing the quality of the solutions. Experimental results show that SPTA has a better routability estimation compared with the existing algorithms.

System-architecture design optimization of flow-based microfluidic biochips has been extensively investigated over the past decade. Most of the prior work, however, is still based on chip architectures with dedicated storage units and this, not only limits the performance of biochips, but also increases their fabrication cost. To overcome this limitation, a distributed channel-storage architecture can be implemented, where fluid samples can be cached temporarily in flow channels instead of using a dedicated storage. This new concept of fluid storage, however, requires a careful arrangement of fluid samples to enable the channels to fulfill the dual functions of transportation and caching. Moreover, to avoid cross-contamination between different fluidic flows, wash operations are necessary to remove the residue left in flow channels. In this article, we formulate the first practical system level design and wash optimization problem for microfluidic biochips with distributed channel storage architecture, considering high-level synthesis, physical design, and wash optimization simultaneously, and present a top-down design flow to solve this problem systematically. Given the protocol of a biochemical application and the corresponding design requirements, our goal is to generate a chip architecture with low fabrication cost. Meanwhile the biochemical application can be executed efficiently with an optimized wash scheme. Experimental results on multiple benchmarks confirm that our approach leads to short completion time of biochemical applications, low chip cost, as well as high wash efficiency.

Recent advances in continuous-flow microfluidics have enabled highly integrated lab-on-a-chip biochips. These chips can execute complex biochemical applications precisely and efficiently within a tiny area, but they require a large number of control ports and the corresponding control logic to generate required pressure patterns for flow control, which, consequently, offset their advantages and prevent their wide adoption. In this article, we propose the first flow-control layer co-synthesis flow called MiniControl, for continuous-flow microfluidic biochips under strict constraints for control ports, incorporating high-level synthesis, physical design, and control system design simultaneously, which has never been considered in previous work. With the maximum number of allowed control ports specified in advance, this synthesis flow aims to generate biochip architectures with high execution efficiency and the corresponding control systems with optimized timing performance. Besides, the overall cost of a biochip can be reduced and the tradeoff between a control system and execution efficiency of biochemical applications can be evaluated for the first time. The experimental results demonstrate that MiniControl leads to high execution efficiency, low platform cost, as well as excellent timing performance, while strictly satisfying the given control-port constraints.

Continuous-flow microfluidic biochips have attracted high research interest over the past years. Inside such a chip, fluid samples of milliliter volumes are efficiently transported between devices (e.g., mixers, heaters, etc.) to automatically perform various laboratory procedures in biology and biochemistry. Each transportation task, however, requires an exclusive flow path composed of multiple contiguous microchannels during its execution period. Excess/waste fluids, in the meantime, should be discarded by independent flow paths connected to waste ports. All these paths are etched in a very tiny chip area using multilayer soft lithography and driven by flow ports connecting with external pressure sources, forming a highly integrated chip architecture that determines the final performance of biochips. In this article, we propose a new and practical design flow called PathDriver+ (PD+) for the architecture design of microfluidic biochips, integrating the actual fluid manipulations into both high-level synthesis and physical design, which has never been considered in prior work. With this design flow, highly efficient chip architectures with a flow-path network that enables the actual fluid transportation and removal can be constructed automatically. Meanwhile, fluid volume management between devices and flow-path minimization are realized for the first time, thus, ensuring the correctness of assay outcomes while reducing the complexity of chip architectures. Additionally, diagonal channel routing is implemented to fundamentally improve the chip performance. The tradeoff between the numbers of channel intersections and fluidic ports is evaluated to further reduce the fabrication cost of biochips. The experimental results on multiple benchmarks confirm that the proposed design flow leads to high assay execution efficiency and low overall chip cost.

Interconnect delay is a key factor that affects the chip performance in layer assignment. Particularly in the advanced process technologies of 5 nm and beyond, interconnect delay has grown significantly due to the increase of circuit scale. Moreover, coupling effect existed in wires reduces the accuracy of delay evaluation. On the other hand, the size of vias is often ignored in layer assignment, which enlarges the mismatch between global routing and detailed routing. To solve these problems, we proposeVPT, a timing-aware layer assignment algorithm considering via pillars, which includes the following five key techniques: 1) via pillar structure combined with nondefault-rule (NDR) wires is adopted to form a net delay optimization system for advanced process technologies; 2) a synthetical model that can adapt to varying types and sizes of both vias and wires is designed to evaluate overflow effectively; 3) a sorting strategy is devised to reduce uncertainty of layer assignment flow and improve stability of the proposed algorithm; 4) an awareness strategy based on multiaspect congestion assessment is designed to reduce overflow significantly; and 5) a net scalpel algorithm is devised to minimize the maximum delay of nets, so that the timing behaviors can be improved systematically. The experimental results on multiple benchmarks confirm that the proposed algorithm leads to lower delay and less overflow, while achieving the best solution quality among the existing algorithms with the shortest runtime.

Programmable microfluidic devices (PMDs) have emerged as a new software-controlled architecture for next-generation flow-based biochips. These devices can be dynamically reconfigured to perform different bioassays flexibly and efficiently owing to their 2-D regularly arranged valve structure. However, PMDs are confronted with critical contamination issues due to the matrix-like structure with intersecting channels. In this article, a block-flushing method is proposed for contamination removal, based on which an overall contamination-aware synthesis flow is proposed. In the proposed block-flushing approach, contaminated areas are first collected according to specific patterns and then flushed as a whole to increase washing efficiency. Then, the synthesis flow integrating the block-flushing method is further optimized such that functional bioassay operations and washing operations can be performed simultaneously for higher efficiency. Experimental results demonstrate that the proposed washing approach reduces the washing time by 28% on commonly used bioassays. Equipped with the proposed washing method, our contamination-aware synthesis flow effectively reduces 30% of the completion time of the bioassays compared with the baseline method.

In digital circuit designs, sequential components such as flip-flops are used to synchronize signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages. Although this fully synchronous style can reduce design efforts significantly, it may affect circuit performance negatively, because sequential components can only introduce delays into signal propagations but never accelerate them. In this article, we propose a new timing model, VirtualSync+, in which signals, specially those along critical paths, are allowed to propagate through several sequential stages without flip-flops. Timing constraints are still satisfied at the boundary of the optimized circuit to maintain a consistent interface with existing designs. By removing clock-to-q delays and setup time requirements of flip-flops on critical paths, the performance of a circuit can be pushed even beyond the limit of traditional sequential designs. In addition, we further enhance the optimization with VirtualSync+ by fine-tuning with commercial design tools, e.g., design compiler from Synopsys, to achieve more accurate result. To achieve this fine-tuning, we first optimize the circuits by reallocating sequential components with sequential and combinational components as delay units. Afterward, the removal locations of flip-flops with respect to the circuits under optimization are extracted and the corresponding wave-pipelining timing constraints compatible with commercial design tools are established. These timing constraints are then incorporated into the optimization flow of commercial tools to generate the optimized circuits. The experimental results demonstrate that circuit performance can be improved by up to 4% (average 1.5%) compared with that after extreme retiming and sizing, while the increase of area is still negligible. This timing performance is enhanced beyond the limit of traditional sequential designs. It also demonstrates that compared with those after retiming and sizing, the circuits with VirtualSync+ can achieve better timing performance under the same area cost or smaller area cost under the same clock period, respectively.

As an emerging lab-on-a-chip technology platform, digital microfluidic biochips (DMFBs) have been widely used for executing various laboratory procedures in biochemistry and biomedicine such as gene sequencing and near-patient diagnosis, with the advantages of low reagent consumption, high precision, and miniaturization and integration. With the ongoing rapid deployment of DMFBs, however, these devices are now facing serious and complicated security challenges that not only damage their functional integrity but also affect their system reliability. In this article, we present a systematic review of DMFB security, focusing on both the state-of-the-art attack and defense techniques. First, the overall security situation, the working principle, and the corresponding fabrication technology of DMFBs are introduced. Afterwards, existing attack approaches are divided into several categories and discussed in detail, including denial of service, intellectual property piracy, bioassay tampering, layout modification, actuation sequence tampering, concentration altering, parameter modification, reading forgery, and information leakage. To prevent biochips from being damaged by these attack behaviors, a number of defense measures have been proposed in recent years. Accordingly, we further classify these techniques into three categories according to their respective defense purposes, including confidentiality protection, integrity protection, and availability protection. These measures, to varying degrees, can provide effective protection for DMFBs. Finally, key trends and directions for future research that are related to the security of DMFBs are discussed from several aspects, e.g., manufacturing materials, biochip structure, and usage environment, thus providing new ideas for future biochip protection.

Memristor-based crossbars are considered to be promising candidates to accelerate vector-matrix computation in deep neural networks. Before being applied for inference, mem-ristors in the crossbars should be programmed to conductances corresponding to the network weights after software training. Existing programming methods, however, adjust conductances of memristors individually with many programming-reading cycles. In this paper, we propose an efficient programming framework for memristor crossbars, where the programming process is partitioned into the predictive phase and the fine-tuning phase. In the predictive phase, multiple memristors are programmed simultaneously with a memristor programming model and IR-drop estimation. To deal with the programming inaccuracy resulting from process variations, noise and IR-drop and move conductances to target values, memristors are fine-tuned afterwards to reach a specified programming accuracy. Simulation results demonstrate that the proposed method can reduce the number of programming-reading cycles by up to 94.77% and 90.61% compared to existing one-by-one and row-by-row programming methods, respectively.

As the scale of VLSI circuits increases rapidly, multi-FPGA prototyping systems have been widely used for logic verification. Due to the limited number of connections between FPGAs, however, the routability of prototyping systems is a bottleneck. As a consequence, timing division multiplexing (TDM) technique has been proposed to improve the usability of prototyping systems, but it causes a dramatic increase in system delay. In this paper, we propose ALIFRouter, a practical architecture-level inter-FPGA router, to improve the chip performance by reducing the corresponding system delay. ALIFRouter consists of three major stages, including i) routing topology generation, ii) TDM ratio assignment, and iii) system delay optimization. Additionally, a multi-thread parallelization method is integrated into the three stages to improve the efficiency of ALIFRouter. With the proposed algorithm, major performance indicators of multi-FPGA systems such as signal multiplexing ratio can be improved significantly.

The emergence of continuous-flow microfluidics has led to a revolution in biochemistry and biomedicine. On such a microscale lab-on-a-chip system, complex biochemical assays, e.g., DNA analysis and drug discovery, can be executed efficiently without any human intervention. Owing to the high complexity of chip architecture and assay protocol, considerable effort has been directed towards the design automation of such chips over the past decade. Existing methods, however, perform the corresponding design tasks including binding, scheduling, placement, and routing separately, leading to serious gaps between different steps and may even cause design failure. To overcome these drawbacks, in this paper, we propose a one-pass architecture synthesis flow called BigIntegr, for continuous-flow microfluidic lab-on-a-chip, integrating all the design steps into an “organic whole”, which has never been considered in prior work. With the proposed BigIntegr, the aforementioned design tasks can be synchronized seamlessly and performed in a combined manner, thereby eliminating the gaps between design steps. As a result, biochip architectures with both high efficiency and low cost can be generated without any design adjustments and modifications. Experimental results on multiple benchmarks demonstrate the effectiveness of the proposed automation flow.

Flow-based microfluidic biochips have attracted much attention in the EDA community due to their miniaturized size and execution efficiency. Previous research, however, still follows the traditional computing model with a dedicated storage unit, which actually becomes a bottleneck of the performance of biochips. In this article, we propose a distributed channel-storage architecture (DCSA) to cache fluid samples inside flow channels temporarily. Since distributed storage can be accessed more efficiently than a dedicated storage unit and channels can switch between the roles of transportation and storage easily, biochips with this architecture can achieve a higher execution efficiency even with fewer resources. Furthermore, we also address the flow-path planning that enables the manipulation of actual fluid transportation/caching on a chip. The simulation results confirm that the execution efficiency of a bioassay can be improved significantly, while the number of valves in the biochip can be reduced accordingly. Also, flow paths for transportation tasks can be constructed and planned automatically with minimum extra resources.

Layer assignment, a major step in global routing of integrated circuits, is usually performed to assign segments of nets to multiple layers. Besides the traditional optimization goals such as overflow and via count, interconnect delay plays an important role in determining chip performance and has been attracting much attention in recent years. Accordingly, in this paper, we propose MiniDelay, a timing-aware layer assignment algorithm to minimize delay for advanced technology nodes, taking both wire congestion and coupling effect into account. MiniDelay consists of the following three key techniques: 1) a non-default-rule routing technique is adopted to reduce the delay of timing critical nets, 2) an effective congestion assessment method is proposed to optimize delay of nets and via count simultaneously, and 3) a net scalpel technique is proposed to further reduce the maximum delay of nets, so that the chip performance can be improved in a global manner. Experimental results on multiple benchmarks confirm that the proposed algorithm leads to lower delay and few vias, while achieving the best solution quality among the existing algorithms with the shortest runtime.

Recent advances in resistive synaptic devices have enabled the emergence of brain-inspired smart chips. These chips can execute complex cognitive tasks in digital signal processing precisely and efficiently using an efficient neuromorphic system. The neuromorphic synapses used in such chips, however, are very sensitive to the external environment, thereby weakening their resistance to malicious modifications such as hardware Trojans and backdoors. Accordingly, in this paper, we propose HTcatcher, a security verification technique for hardware threat detection in neuromorphic computing systems, incorporating finite state machine and feature verification simultaneously, which has never been considered in prior work. Furthermore, we propose a pseudo-random matrix verifying technique for memory optimization, which can reduce the memory overhead of the multi-dimensional features in the system significantly. Experimental results confirm that the proposed method can identify the malicious modifications in the system accurately, while reducing the memory usage by 25%-50%.

As the scale of VLSI circuits and fabrication costs increase rapidly, multi-FPGA prototyping systems are widely adopted in industry to make logic verification faster and cheaper. Since routing signals can usually exceed the number of I/O pins in an FPGA, timing division multiplexing (TDM) technique is required to solve this problem. FPGA routing for developing a prototyping system is a big challenge due to the signal delay of TDM. This paper presents MSFRoute, a multi-stage FPGA routing framework for timing division multiplexing technique, to optimize the signal delay and the routability for prototyping systems. In this work, a TDM ratios assignment algorithm with an efficient parallelization method is proposed to optimize inter-FPGA signal delay. Meanwhile, we propose a practical system clock period optimization method to solve critical signal delay problem. Experimental results show that our routing framework reduces TDM ratios by up to 88.3% with an average reduction rate of 41.8%. With the proposed parallelization method, total flow of MSFRoute can get up to 4.38X speedup with a 2.77X speedup on average.

Continuous-flow microfluidic biochips have attracted high research interest over the past years. Inside such a chip, fluid samples of milliliter volumes are efficiently transported between devices (e.g., mixers, etc.) to automatically perform various laboratory procedures in biology and biochemistry. Each transportation task, however, requires an exclusive flow path composed of multiple contiguous microchannels during its execution period. Excess/waste fluids, in the meantime, should be discarded by independent flow paths connected to waste ports. All these paths are etched in a very tiny chip area using multilayer soft lithography and driven by flow ports connecting with external pressure sources, forming a highly integrated chip architecture that dominates the performance of biochips. In this paper, we propose a practical synthesis flow called PathDriver for the design automation of microfluidic biochips, integrating the actual fluid manipulations into both high-level synthesis and physical design, which has never been considered in prior work. Given the protocols of biochemical applications, PathDriver aims to generate highly efficient chip architectures with a flow-path network that enables the manipulation of actual fluid transportation and removal. Additionally, fluid volume management between devices and flow-path minimization are realized for the first time, thus ensuring the correctness of assay outcomes while reducing the complexity of chip architectures. Experimental results on multiple benchmarks demonstrate the effectiveness of the proposed synthesis flow.

The emergence of flow-based microfluidic biochips (FBMBs) has increased the automation level of biochemical procedures, and these lab-on-a-chip devices are now being used for enzyme-linked immunosorbent assay, point-of-care diagnosis, etc. As fabrication technology advances, the feature size of FBMBs keeps shrinking, thereby introducing a series of knotty challenges to the physical design of FBMBs. In particular, timing-sensitive bioassays, such as forensic DNA typing and chromatin immunoprecipitation, require a highly accurate time-control of fluids within a limited completion time. However, existing work does not consider the real-time requirements of these bioassays. In this paper, we formulate the first practical timing-driven flow-channel network construction problem for FBMBs and present a performance-driven placement and routing algorithm for solving this problem. Given the design specifications of a biochip and its biochemistry application, our goal is to construct a high-quality flow-channel network with minimized timing delay and total cost. The experimental results on 14 benchmarks confirm that our algorithm leads to better timing behavior and lower chip cost.

Flow-based microfluidic biochips are one of the most promising platforms used in biochemical and pharmaceutical laboratories due to their high efficiency and low costs. Inside such a chip, fluids of nanoliter volumes are transported between devices for various operations, such as mixing and detection. The transportation channels and corresponding operation devices are controlled by microvalves driven by external pressure sources. Since assigning an independent pressure source to every microvalve would be impractical due to high costs and limited system dimensions, states of microvalves are switched by a control logic using time multiplexing. Existing control-logic designs, however, still switch only a single control channel per operation, leading to a low efficiency. In this article, we present the first automatic synthesis approach for a control logic that is able to switch multiple control channels simultaneously. Moreover, we propose the first fault-aware design in control logic by introducing backup control paths to maintain the correct function even when manufacturing defects occur. The construction of control logic is achieved by a highly efficient framework based on particle swarm optimization, Boolean logic simplification, grid routing, together with mixing multiplexing. The simulation results demonstrate that the proposed multichannel switching mechanism leads to fewer valve-switching times and lower total logic cost, while realizing fault tolerance for all control channels.

Recent advances in continuous-flow microfluidics have enabled highly integrated lab-on-a-chip biochips. These chips can execute complex biochemical applications precisely and efficiently within a tiny area, but they require a large number of control ports and the corresponding control logic to generate required pressure patterns for flow control, which, consequently, offset their advantages and prevent their wide adoption. In this paper, we propose the first synthesis flow called MiniControl, for continuous-flow microfluidic biochips (CFMBs) under strict constraints for control ports, incorporating high-level synthesis and physical design simultaneously, which has never been considered in previous work. With the maximum number of allowed control ports specified in advance, this synthesis flow generates a biochip architecture with high execution efficiency. Moreover, the overall cost of a CFMB can be reduced and the tradeoff between control logic and execution efficiency of biochemical applications can be evaluated for the first time. Experimental results demonstrate that MiniControl leads to high execution efficiency and low overall platform cost, while satisfying the given control port constraint strictly.

Flow-based microfluidic biochips (FBMBs) have attracted much attention over the past decade. On such a micrometer-scale platform, various biochemical applications, also called bioas-says, can be processed concurrently and automatically. To improve execution efficiency and reduce fabrication cost, a distributed channel-storage architecture (DCSA) can be implemented on this platform, where fluid samples can be cached temporarily in flow channels close to components. Although DCSA can improve the execution efficiency of FBMBs significantly, it requires a careful arrangement of fluid samples to enable the channels to fulfill the dual functions of transportation and caching. In this paper, we formulate the first flow-layer physical design problem considering DCSA, and propose a top-down synthesis algorithm to generate efficient solutions considering execution efficiency, washing, and resource usage simultaneously. Experimental results demonstrate that the proposed algorithm leads to a shorter execution time, less flow-channel length, and a higher efficiency of on-chip resource utilization for biochemical applications compared with a direct approach to incorporate distributed storage into existing frameworks.

Electrowetting-on-dielectric (EWOD) is a mechanism that allows physical handling of liquids with only electrical signals, such as digitizing a liquid into tiny droplets and manipulating them on a chip, thus enabling “digital microfluidics”. As an elegantly simple platform free of pumps or valves, EWOD digital microfluidics has been attracting high research interest in the past two decades and has recently been transitioned to a few commercial products in displays and biochemistry. However, the number of labs utilizing this technology is still small, due to the difficulty in translating design intent to manufactured devices. Accordingly, in this paper, we propose a cloud-based open-source EWOD cybermanufacturing ecosystem that enables an automatic translation from user requirements to manufactured digital microfluidics. The incubation cyber ecosystem is to be accessible to a wide range of end users, allowing researchers, entrepreneurs, students, and hobbyists alike to focus on their own ideas and applications without having to master the subtleties of EWOD engineering and manufacturing. This can be thought of as an “operating system” for EWOD community, similar to Windows and macOS for people with no computer hardware background. The proposed cyber ecosystem aims to ease the process of designing and eliminate the burden of fabricating EWOD chips so that the user pool is increased and more applications found for EWOD digital microfluidics.

With the sharp increase of very large-scale integrated (VLSI) circuit density, we are faced with many knotty issues. Particularly in the routing phase of VLSI physical design, the interconnection effects directly relate to the final performance of circuits. However, the optimization capability of traditional rectilinear architecture is limited; thus, both academia and industry have been devoted to nonrectilinear architecture in recent years, especially octilinear architecture, which is the most promising because it can greatly improve the performance of modern chips. In this article, we design FH-OAOS, an obstacle-avoiding algorithm in octilinear architecture, by constructing an obstacle-avoiding the octilinear Steiner minimal tree (OAOSMT). Our approach first constructs an obstacle-free Euclidean minimal spanning tree (OFEMST) on the given pins based on Delaunay triangulation (DT). Then, two lookup tables about OFEMST’s edge are generated, which can be seen as the information center of FH-OAOS and can provide information support for algorithm operation. Next, an efficient obstacle-avoiding strategy is proposed to convert the OFEMST into an obstacle-avoiding octilinear Steiner tree (OAOST). Finally, the generated OAOST is refined to construct the final OAOSMT by applying three effective strategies. Experimental results on various benchmarks show that FH-OAOS achieves 66.39 times speedup on average, while the average wirelength of the final OAOSMT is only 0.36% larger than the best existing solution.

As the basic model for very large scale integration routing, the Steiner minimal tree (SMT) can be used in various practical problems, such as wire length optimization, congestion, and time delay estimation. In this paper, an effective algorithm based on particle swarm optimization is presented to construct a multilayer obstacle-avoiding X-architecture SMT (ML-OAXSMT). First, a pretreatment strategy is presented to reduce the total number of judgments for the routing conditions around obstacles and vias. Second, an edge transformation strategy is employed to make the particles have the ability to bypass the obstacles while the union-find partition is used to prevent invalid solutions. Third, according to the feature of ML-OAXSMT problem, we design an edge-vertex encoding strategy, which has the advantage of simple and effective. Moreover, a penalty mechanism is proposed to help the particle bypass the obstacles, and reduce the generation of via at the same time. Experimental results show that our algorithm from a global perspective of multilayer structure can achieve the best solution quality among the existing algorithms. Finally, to our best knowledge, we redefine the edge cost and then construct the obstacle-avoiding preferred direction X-architecture Steiner tree, which is the first work to address this problem and can offer the theory supports for chip design based on non-Manhattan architecture.

Obstacle-avoiding Steiner minimal tree (OASMT) construction has become a focus problem in the physical design of modern very large-scale integration (VLSI) chips. In this article, an effective algorithm is presented to construct an OASMT based on X-architecturex for a given set of pins and obstacles. First, a kind of special particle swarm optimization (PSO) algorithm is proposed that successfully combines the classic genetic algorithm (GA), and greatly improves its own search capability. Second, a pretreatment strategy is put forward to deal with obstacles and pins, which can provide a fast information inquiry for the whole algorithm by generating a precomputed lookup table. Third, we present an efficient adjustment method, which enables particles to avoid all the obstacles by introducing some corner points of obstacles. Finally, an excellent refinement method is discussed to further enhance the quality of the final routing tree, which can improve the quality of the solution by 7.93% on average. To our best knowledge, this is the first time to specially solve the single-layer obstacle-avoiding problem in X-architecture. Experimental results show that the proposed algorithm can further shorten wirelength in the presence of obstacles. And it achieves the best solution quality in a reasonable runtime among the existing algorithms.