An optimized Ternary CAM concept is introduced for the hardware search engines in high-speed Internet routers. Our design employs w + 1 RAM bits to store a word of size w, whereas a conventional TCAM needs 2w RAM bits for the same word size. Based on this concept an 8-bit cluster is designed out of 9 SRAM bits, used as the basic building block of our Prefix-CAM (PCAM) structure. Four such clusters merge to store a 32-bit IPv4 prefix, thus, configuring a PCAM suitable for Internet packet forwarding. This PCAM module employs 48% less SRAM cells and a total of 22% less transistors plus 50% less address decode interconnects compared to a conventional TCAM, for equal storage size and equal functionality. We show that PCAM can be employed for multifield packet classification. Other factors, such as lookup speed and power dissipation, are not adversely affected.

A novel low power ripple-precharge ternary CAM (RP-TCAM) architecture is proposed for applications in longest prefix matching tasks. The main motivation behind this research is to reduce the dynamic power consumption in TCAM due to frequent charging and discharging of the highly capacitive match line. This issue is addressed by exploiting the fact that when we compare only the first four bits of incoming packet's destination address we can identify up to 80% mismatches in the forwarding table. A selective precharge scheme was devised exploiting the above fact wherein the match line is charged only when there is an exact match in the first four bits of TCAM word, thereby significantly reducing the number of transitions in the match line. The parasitics for simulation were extracted from the layout implemented for a 64 /spl times/ 32 RP-TCAM architecture using 0.18/spl mu/m technology. This structure has 1.71% less area and 80% less power when compared to the conventional TCAM of equal storage size and functionality. Our RP-TCAM architecture has a search time of 1.86ns.

We present a search algorithm implementable by a parallel architecture based on partitioned forwarding table. This scheme effectively reduces the complexity of finding "the longest prefix match" problem to "a prefix match" problem. The main feature of this algorithm is twofold. First, it advocates intelligent partitioning of the forwarding table to enhance and parallelize the lookup operation. Second, it takes advantage of ternary CAM to achieve low lookup time. The resulting architecture has better throughput and much better update time than the traditional TCAM. Our experimental results show that such features can significantly elevate the flexibility and scalability of the next generation packet processing devices.

We propose a novel approach for IP packet forwarding based on a new ternary content addressable memory configuration. Our design is an efficient hardware solution for the longest prefix matching problem in Internet routers. Our scheme segregates the encompassing prefixes into a separate, practically small TCAM module. Consequently, the remaining prefixes, that often conform to more than 92% of the lookup table, form a disjoint set. The big TCAM module that accommodates this set has a simplified architecture, with no priority encoder. Our architecture has lower update complexity, lower cost and shorter search time, compared to the conventional TCAM structure.

An optimized ternary CAM concept is introduced for application in the longest prefix matching tasks of the Internet search engines. It employs w+1 RAM bits for a word of size w. A conventional TCAM needs 2w RAM bits for the same word size. Based on this concept an 8 bit prefix-CAM cluster is designed out of 9 SRAM bits, four of which merge to store a 32-bit IPv4 prefix. A complete prefix-CAM module employs 22% less transistors than a conventional TCAM, for equal storage size and equal functionality. We confirm the 22% area saving by implementing the layouts for prefix-CAM and TCAM words. Our design also reduces interconnect area by reducing address decode lines.

In this paper, we introduce the idea of using packet switched network as the mode of communication between automatic test equipment and the VLSI chip under test in a multisite ATE architecture. We show that our architecture, which we refer to as test area network reduces the complexity and time involved in testing tens of chips at a time. To increase the ATE utilization, we distribute a portion of ATE's task of signature verification to the intelligent test-heads, which are now capable of applying patterns and verifying signatures produced by the chip being tested. Our analysis and empirical results indicate a speed up of 4 to 10 by using existing network infrastructure.

In this paper, we present a fully scalable architecture for IP packet forwarding engines used in router line cards and other network equipment. Our conceptually sliced architecture can be replicated to increase the number of ports or deal with larger lookup tables. We show empirical evidence that, using our architecture, the expansion requires very limited glue logic and does not deteriorate the performance. Such a scalability feature is especially vital to satisfy the Internet's huge appetite for large routing tables, increased traffic, higher speed and the migration to IPv6.

We present an efficient IP packet forwarding methodology and architecture. This is achieved by partitioning the lookup table into smaller ones for each output port and allowing a forwarding engine to process them in parallel. This effectively reduces the complexity of the problem of finding "the longest prefix match" to that of finding "the first prefix match".

A reconfigurable memory architecture and lookup technique for IP packet forwarding engines is presented. This is a flexible technique that significantly elevates the scalability of the next generation network processors and other packet processing equipments, especially in terms of increased routing table sizes, increased traffic and bandwidth, increased frequency of route updates, and migration to IPv6.