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Chi-Ping Hsu

dblp:18/2269 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Electronic design automation · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
physical design		 0.041988
Proud: A Fast Sea-of-Gates Placement Algorithm · DAC 1988
Minimum-Via Topological Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
General river routing algorithm · DAC 1983
Electronic design automation › physical design
routing		 0.031983
Minimum-Via Topological Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
General river routing algorithm · DAC 1983
A new two-dimensional routing algorithm · DAC 1982
Electronic design automation › physical design › placement
circuit placement		 0.011988
Proud: A Fast Sea-of-Gates Placement Algorithm · DAC 1988
Electronic design automation › physical design › routing › multilayer routing
layer assignment		 0.011983
Minimum-Via Topological Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › physical design › routing › channel routing
river routing		 0.011983
General river routing algorithm · DAC 1983
Electronic design automation › physical design › routing › VLSI routing
topological routing		 0.011983
Minimum-Via Topological Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › physical design › routing
via minimization		 0.011983
Minimum-Via Topological Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › physical design › routing › VLSI routing
two-dimensional routing		 0.011982
A new two-dimensional routing algorithm · DAC 1982

Methods — techniques the papers use, named apart from their topics

maximum-cut formulation · 0.0greedy algorithm · 0.0
YearPublicationVenuePosition
1988 Proud: A Fast Sea-of-Gates Placement Algorithm
Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu
 DAC3
1983 General river routing algorithm
Chi-Ping Hsu
 DAC1
1983 Minimum-Via Topological Routing
abstract
A new approach to the two-dimensional routing utilizing two layers is proposed. It consists of two major steps, topological routing and geometrical mapping. This paper describes the topological routing algorithm in detail. Based on a circle graph representation of the net intersection information of the routing problem, a maximal set of nets that can be routed without vias are selected. The layer assignments for the selected nets are determined by a global analysis so that the total number of vias needed is minimum. The layer assignment problem turns out to be a maximum-cut problem on an edge-weighted graph and we developed a greedy algorithm for it. According to the layer assignments, the detailed topological routes are then generated.
Chi-Ping Hsu
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1982 A new two-dimensional routing algorithm
Chi-Ping Hsu
 DAC1