In a realistic register-transfer-level component library, there usually exist several different hardware implementations for one generic function. This gives rise to a large design space of component selection which is interleaved with the scheduling of operations. Previous methods ignored the presence of multicomponent selection in the process of lower/upper hound estimation of scheduling, and produced the local lower/upper bounds which would cause the suboptimum designs. Opposite to the previous methods, we compute, in this paper, the lower/upper bounds which consider scheduling and component selection simultaneously. A new problem of multicomponent selection integrated with interval scheduling is studied. We present a very interesting and important result that both the lower bound and upper bound of multicomponent selection are obtained on the most cost-effective components which have the minimum area-delay products. This property leads to the fact that the lower bound and upper bound of multicomponent selection can be calculated efficiently. An integer linear programming model and a surrogate relaxation technique are proposed to derive an optimum surrogate lower bound which has an asymptotic performance ratio less than two for a single type of function. An upper bound with the same asymptotic performance ratio is also obtained which turns out to be the optimum solution value of the traditional unicomponent selection with the most cost-effective components. Both the theoretical analysis and the experimental results show that the performance of the bounds are very promising.

This paper shows how algorithmic techniques and parallel processing can speed up general connectivity computation. A new algorithm, called Concurrent Group Search Algorithm (CGSA), is proposed that divides N(N-1)/2 vertex pairs into N-1 groups. Within each group general connectivities of all pairs can be calculated concurrently. Our experimental results show that this technique can achieve speedup of 12 times for one circuit. In addition, group computations are parallelized on a 16-node IBM SP2 with a speedup of 14 times over its serial counterpart observed. Combining the two approaches could result in a total speedup of up to 170 times, reducing CPU time from over 200 hours to 1.2 hour for one circuit. Our new model is better than those without clustering because it characterizes the connection graph more accurately, is faster to compute and produces better results. The best performance improvements are 43% for one circuit and 49% for another.