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P. V. Ananda Mohan

dblp:18/2724 · also Pemmaraju V. Ananda Mohan · DBLP profile ↗
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5ranked-venue papers
3as first author
0since 2021 · last 2008
0000-0002-7246-0108ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits
active filter design		 0.021987
New structures for MOSFET-C filters · Proc. IEEE 1987
Active filter design using cascaded identical low-order (≥ 2) filter sections · Proc. IEEE 1985
Integrated circuit design
analog and mixed-signal circuits		 0.021987
New structures for MOSFET-C filters · Proc. IEEE 1987
Active filter design using cascaded identical low-order (≥ 2) filter sections · Proc. IEEE 1985

Methods — techniques the papers use, named apart from their topics

nodal voltage simulation · 0.0pole-q analysis · 0.0cascade synthesis · 0.0
YearPublicationVenuePosition
2008 Implementation of AES S-Boxes using combinational logic
abstract
In this paper, two approaches for implementation of the 8-bit S-Box suitable for FPGA based solutions are considered. These use (a) synthesis of the logic functions using Boolean simplification of the truth table of all the columns and (b) synthesis of the ANF (Algebraic Normal form) logic functions using AND and EXOR gates. The hardware and computation time evaluation for both the options are also presented.
Rashmi Ramesh Racch, P. V. Ananda Mohan
 ISCAS2
1994 Novel Design for Binary to RNS Converters
abstract
The choice of moduli for efficient design of binary-to-RNS converters based on recently proposed algorithms is considered.>
P. V. Ananda Mohan
 ISCAS1
1993 Novel oversampled A/D converters based on error spectrum shaping
Y. V. Ramana Rao, P. V. Ananda Mohan
 ISCAS2
1987 New structures for MOSFET-C filters
abstract
The nodal voltage simulation technique described for generating new active RC filters has been shown to be applicable to the derivation of MOSFET-C filters from active RC filters. The application of the method to Tarmy-Ghausi active RC filter is considered. Further, two MOSFET-C biquads based on the Tow-Thomas active RC biquad are proposed.
P. V. Ananda Mohan
 Proc. IEEE1
1985 Active filter design using cascaded identical low-order (≥ 2) filter sections
abstract
The realization of sharp cutoff filter specifications requires approximation functions with large pole-Qs, while implemented in cascade-form structures. This letter suggests a design approach using identical low-order structures requiring much lower pole-Qs for the constituent second-order blocks.
P. V. Ananda Mohan
 Proc. IEEE1