We address the problem of verifying that a tree is connected using probe operations which check mutual connectivity between two (or more) leaves of the tree. We present optimal algorithms for determining minimal probe sets that detect all possible edge and vertex faults in arbitrary trees. Our results are of particular interest for the testing of interconnection substrates in VLSI multichip module packaging technologies. © 1998 John Wiley & Sons, Inc. Networks 32: 189–197, 1998

A fundamental timing analysis problem in the veri cation and synthesis of interface logic circuitry is the determination of allowable time separations, or skews between interface events, given timing constraints and circuit propagation delays.These skews are used to verify timing properties and determine allowable propagation delays for logic synthesis.This paper presents an algorithm that provides tighter skew bounds with better asymptotic running time than previous methods, and sho ws how to apply the method to synthesis tasks.