Although many physical limitations have been reached in modern micro-lithography, printed critical dimensions continue to shrink according to the International Technology Roadmap for Semiconductors (ITRS) [1]. To meet the demands imposed by this guideline, the traditional separation between design and manufacturing communities is being bridged. Many EDA tools package manufacturing data for delivery into established simulation engines for design verification. However, none of them provide practical implementations of design optimizations at an early stage in the design flow.This paper presents an automated layout modification flow for metal layers with the goal of enhancing manufacturability. It can easily be deployed in a current custom design flow in a way that is visible to designers. The result of this scheme is improvements to process windows and yield, while minimizing circuit performance detractors. The flow is verified through analyses of both the impact on circuit performance and the benefit to manufacturability. It has been implemented in a state-of-the-art 65 nm chip design. Both silicon yield and electrical performance data are currently being collected and analyzed.

Presents an integrated approach for achieving improved yield ramp and enhanced manufacturing margins for deep sub-micron process technologies. This methodology highlights the combination of design IP for process technology characterization, tailored data reduction and analysis of the design components for data characterization, and fault modeling and extraction for root cause failure determination. This approach enables semiconductor companies to characterize yield loss and improve manufacturing process.