EDBT 2026 Demo / reviewers in the wild / expert
Tai-Ying Jiang
dblp:18/3486
· DBLP profile ↗
4ranked-venue papers
4as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.2 | 2 | 2009 | Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009 Observability Analysis on HDL Descriptions for Effective Functional Validation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007 |
Electronic design automation › hardware verification and test › debugging
design debugging |
0.1 | 1 | 2009 | Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009 |
Electronic design automation › hardware verification and test › design validation
functional validation |
0.1 | 1 | 2007 | Observability Analysis on HDL Descriptions for Effective Functional Validation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007 |
Electronic design automation › hardware verification and test › coverage analysis
observability-based code coverage |
0.1 | 1 | 2007 | Observability Analysis on HDL Descriptions for Effective Functional Validation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007 |
Electronic design automation › hardware verification and test › debugging
bug localization |
0.0 | 1 | 2009 | Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2009 |
Electronic design automation › hardware verification and test › coverage analysis
code coverage |
0.0 | 1 | 2007 | Observability Analysis on HDL Descriptions for Effective Functional Validation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2007 |
Methods — techniques the papers use, named apart from their topics
probabilistic confidence score · 0.1probabilistic observability measure · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | Accurate Rank Ordering of Error Candidates for Efficient HDL Design DebuggingabstractWhen hardware description languages (HDLs) are used in describing the behavior of a digital circuit, design errors (or bugs) almost inevitably appear in the HDL code of the circuit. Existing approaches attempt to reduce efforts involved in this debugging process by extracting a reduced set of error candidates. However, the derived set can still contain many error candidates, and finding true design errors among the candidates in the set may still consume much valuable time. Adebuggingprioritymethod was proposed to speed up the error-searching process in the derived error candidate set. The idea is to display error candidates in an order that corresponds to an individual's degree of suspicion. With this method, error candidates are placed in a rank order based on their probability of being an error. The more likely an error candidate is a design error (or a bug), the higher the rank order that it has. With the displayed rank order, circuit designers should find design errors quicker than with blind searching when searching for design errors among all the derived candidates. However, the currently used confidence score (CS) for deriving thedebuggingpriorityhas some flaws in estimating the likelihood of correctness of error candidates due to themaskingerrorsituation. This reduces the degree of accuracy in establishing adebuggingpriority. Therefore, the objective of this work is to develop a new probabilistic confidence score (PCS) that takes themaskingerrorsituation into consideration in order to provide a more reliable and accuratedebuggingpriority. The experimental results show that our proposed PCS achieves better results in estimating the likelihood of correctness and can indeed suggest adebuggingprioritywith better accuracy, as compared to the CS. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2007 | Observability Analysis on HDL Descriptions for Effective Functional ValidationabstractSimulation-based functional validation is still one of the primary approaches for verifying designs described in hardware description languages. Traditional code coverage metrics do not address the observability issue and may overestimate the extent of functional validation. Observability-based code coverage metric (OCCOM) is the first code coverage metric considering the essential observability issue. However, tags can only be observed or unobserved, providing only two levels of measurement (i.e., 1 and 0). Errors with lower opportunities to be observed may still be judged as observable, thus misleading the verification results. Therefore, instead of extending tag coverage, we develop a probabilistic observability measure and its efficient computation algorithm. Besides being used as a new OCCOM, our new measure can point out hard-to-observe points for inserting assertions to prevent bugs from hiding behind these points. Experimental results show that the detection of the injected errors and the degree of our observability measure are strongly related. The results also show that our fine-grained observability measure is less likely to overestimate the extent of validation with reasonable computation time. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 2005 | An observability measure to enhance statement coverage metric for proper evaluation of verification completenessabstractSimulation based validation approaches are still the primary workhorse for solving the verification problem of getting the initial HDL description correct, especially for large scaled designs. However, most of existing code coverage metrics do not address obsevability issue [2]. Therefore, we intend to provide additional observability measures to statement coverage metric for more proper and realistic evaluation of verification completeness for a HDL design. As compared to OCCOM [1,2,3], our approach estimates a real probabilistic likelihood of propagating erroneous effects without any unreasonable assumptions and can always provide lower bound estimation. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
ASP-DAC | 1 |
| 2002 | Effective Error Diagnosis for RTL Designs in HDLsabstractWe propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that true erroneous statements are included in. The probability of correctness for each potential erroneous statement will be estimated such that the most suspected statements are reported first. Experiments show that the size of error candidates is indeed small and the estimation for the probability of correctness for potential error candidates is accurate. Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou |
Asian Test Symposium | 1 |