This paper presents analytical equations for optimizing feedforward equalizer (FFE) and decision feedback equalizer (DFE) parameters in a wireline receiver to speed up system-level design and simulations. A minimum mean square error (MMSE)-based approach is applied to the receiver model, and a set of equations is developed to co-optimize FFE and DFE taps. The equations consider the noise sources in wireline links, including the sampling clock jitter. It also considers the effect of the noise correlations on the equalizer parameters. For sampling clock jitter, two separate models are developed to distinguish between sampling for discrete-time and continuous-time FFEs (pre-and post-FFE sampling). Then, the translation of jitter noise to voltage noise is carefully investigated. Jitter noise can be either white or correlated. Later, the developed model is modified to generate different variants of MMSE-based approaches to be used in various practical scenarios a designer may face. This includes the equalizer design for maximum likelihood sequence estimation (MLSE)-based receivers and equalizer design with bounded DFE tap magnitude to control undesired side effects such as error propagation. Finally, the use of “tap skipping” to save FFE hardware resources is investigated. The accuracy of models and the performance of each method is justified through simulations and comparing against the LMS adaptation loops.

This paper presents a max-pooling phase detector (PD) designed to significantly reduce power consumption and area compared to conventional baud-rate detectors such as the Mueller-Mueller (MMPD) and Sign-Sign MMPD (SS-MMPD). The PD was originally developed using a convolutional neural network (CNN) model and trained within a machine-learning (ML) framework optimized for the provided training dataset. The design method was completed using a minimum mean square error (MMSE) approach to address discrepancies between training conditions and real-world operation, enabling traditional adaptation methods to enhance the performance and robustness of the PD. Synthesized in the GF 22-nm FD-SOI process, the max-pooling PD consumes 40% less power and occupies 60% less area than a standard SS-MMPD.

A 15-bit low-power incremental ADC is designed for sensor applications. The ADC is designed to be frequency-scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, an opamp with class AB characteristics is used. The design was fabricated in 0.18/μm CMOS and occupies an area of 0.35mm2. Configured to operate at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83μW from a 1.8-V supply. Operating as an incremental converter, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 88.9dB peak SNDR while operating from 1.67S/S to 1.67kS/s and scaling analog power by up to 500 times.

Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. Channel coding can be used to lower the required signal-to-noise ratio for a specific bit error rate in a channel. There are numerous codes that can be used to approach the theoretical Shannon limit, which is the maximum information transfer rate of a communication channel for a particular noise level. However, the complexity of these codes prohibits their use in high-speed inter-chip applications. A low-complexity signaling scheme is proposed here. This method can achieve 3-5-dB coding gain over uncoded four-level pulse amplitude modulation (PAM). The receiver for this signaling scheme along with a regular 4-PAM receiver was designed and implemented in a 0.18-mum standard CMOS technology. Experimental results show that the receiver is functional up to 2.5 Gb/s. This was verified with a bit error rate tester (BERT) and we were able to achieve error free operation at 2.5-Gb/s channel transfer rate. The entire receiver for this scheme consumes 22 mW at 2.5 Gb/s and occupies an area of 0.2 mm2.

Increasing demand for high-speed interchip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. Channel coding can be used to approach the theoretical Shannon limit. Although there are numerous capacity-approaching codes in the literature, the complexity of these codes prohibits their use in high-speed interchip applications. This work studies several suitable coding schemes for chip-to-chip communication and backplane application. These coding schemes achieve 3-dB coding gain in the case of an additive white Gaussian noise (AWGN) model for the channel. In addition, a more realistic model for the channel is developed here that takes into account the effect of crosstalk, jitter, reflection, inter-symbol interference (ISI), and AWGN. Interestingly, the proposed signaling schemes are significantly less sensitive to such interference. Simulation results show coding gains of 5-8 dB for these methods with three typical channel models. In addition, low-complexity decoding architectures for implementation of these schemes are presented. Finally, circuit simulation results confirm that the high-speed implementations of these methods are feasible.

High speed and high resolution ADCs are one of the major blocks in digital communication systems. In this paper, it is shown that by reducing the correlation between the ADC input samples, with the use of a simple analog decorrelator filter, the performance of the ADC is considerably enhanced. For an application of 600 Mb/s data transmission over coaxial cable, this technique shows 2.5 bits improvement. Finally, two circuit architectures are presented for the implementation of the decorrelator in 0.25 /spl mu/m CMOS technology with 2.5 V supply.

We present a globally stable arbitrary-order single-bit delta-sigma modulator architecture with continuous-time loop filtering. Using Lyapunov arguments and the method of equivalent control, it is shown that stability is guaranteed for any input signal with peak magnitude less than L>0, where -L and +L denote the quantization levels. The design augments the conventional delta-sigma modulator with switching feedback and the use of distinct operating modes; the additional circuitry required for the implementation of these stabilizing measures is nominal. For a given noise transfer function and fixed oversampling ratio, the new architecture achieves the same peak signal-to-noise-plus-distortion ratio as a traditional delta-sigma modulator. The proposed design can also yield near-peak performance for inputs which destabilize the conventional delta-sigma data converter. Simulation results are provided for the proposed modulator and a comparable standard interpolative design.

A new technique for tuning high-Q continuous-time filters is presented. This technique is a modified version of an adaptive tuning method where the tuning signals are sinusoids generated by digital bandpass delta sigma oscillators. As will be shown, the required building blocks for the tuning system are simple. Simulation results are presented to show the feasibility of the proposed approach.

With the growing demand for high-speed transmission of digital data, there is a challenge for utilizing the existing copper plant as the transmission medium, especially for short-hop links. This medium offers a lower cost to a fiber medium, but requires more sophisticated electronics to account for electromagnetic emissions, cross-talk, and cable loss. These include pulse shaping filters, cross-talk cancelers, and equalizers. To maintain system cost at a minimum, analog solutions are preferred. A continuous-time tunable biquad implemented in a 0.8 /spl mu/m BiCMOS process and configured as an adaptive pulse-shaping filter is described. The biquad is tunable over the range 10-230 MHz with variable Q factors. It is composed of five transconductance-C integrators each dissipating a static power of 10 mW at 5 V. A method for adapting the filter's pole-frequency and Q-factor while servicing 100 Mb/s NRZ data is presented together with experimental results.

Recently, a new architecture was proposed which utilizes the concept of time-interleaving in oversampling converters. Using this architecture, one is theoretically able to achieve higher resolutions by using an array of interconnected modulators without increasing the oversampling ratio or order of the modulators. Alternatively, the same resolution can be maintained with wider bandwidth input signals. This paper presents the first experimental results on this new family of modulators. As well, the practical issue of component mismatch for these converters are studied and some suggestions are made to alleviate the effects of this problem.>

In many applications, it is desirable to synthesize an adaptive impedance to match some "real world" system, so that when the target impedance changes, the matching impedance tracks this change and maintains a close match. In this paper we present a scheme for adaptive impedance matching formulated in the Model Reference Adaptive Systems' Control (MRAS) framework. The Model Reference adaptive controller can be implemented using Adaptive Delta-Sigma Filters to improve the performance-to-cost ratio due to their inherent oversampling. We will refer to this combined framework for adaptive impedance matching as MRAS/AIM.>

Viterbi detectors have traditionally been realized in digital hardware and/or software. However, analog implementations can lead to smaller, faster and lower power-consumption circuits. In this paper, a new architecture for realizing a class-IV partial-response Viterbi detector is proposed and implemented using simple analog building blocks. This architecture is more robust against offsets and gain errors than other analog detectors and should operate faster when implemented in the same technology. In addition, it is shown that the Viterbi detector is an adaptive-threshold device with a complexity much less than that of a typical 6-bit A/D convertor required in digital realizations. Performance of the detector is evaluated by simulations and experimental results.>

The effects of DC offsets on four variations of the stochastic gradient algorithm are analyzed to determine the most appropriate algorithm for hardware implementation. The output mean squared error (MSE) performance in the presence of DC offsets is evaluated and compared with computer simulations for each of the algorithms assuming a Gaussian input distribution.>