There has recently been a significant growth in resource-constrained devices (RCDs) that exchange sensitive and private data. Lightweight ciphers are designed to implement confidentiality in RCDs. Hardware implementation of lightweight cipher should minimize resources, including area, power, and energy. Hardware Trojans (HTs) are malicious circuits that are inserted into designs, including lightweight ciphers, to modify cipher behavior and leak sensitive data. Although runtime monitoring is a very effective method to implement design-for-trust and detect hardware trojans, it requires significant resources and degrades performance. The main motivation of this research is to design RCD-friendly runtime monitoring and create a trusted design with minimal resource overhead. This article develops a low-power, low-energy and trusted design based on a smart runtime monitoring algorithm targeted for lightweight ciphers in RCDs, implemented in the FPGA platform. The algorithm is adaptive, minimizes resource, and maximizes confidence and HT detection. The novelties of the algorithm are its adaptive activation of checking and its validation. Checking is triggered when a predefined critical node is active, which limits power/energy overhead. Our proposed algorithm has adaptive positive aging because it forgoes validation when a critical node has been already proven safe. To optimize trust, the validation uses a reverse-function design. The implementation results show that proposed algorithm reduces area, power and energy, when compared with existing algorithms. The proposed algorithm achieves 37%–55% reduction in energy and power, and has an average of 53% improvement in LE×energy metric. Furthermore, our proposed algorithm reduces the area by 25% when both encryption and decryptions are implemented.

Abstract The growth of low‐resource devices has increased rapidly in recent years. Communication in such devices presents two challenges: security and resource limitation. Lightweight ciphers, such as HIGHT cipher, are encryption algorithms targeted for low resource systems. Designing lightweight ciphers in reconfigurable platform (e.g., field‐programmable gate array) provides speedup as well as flexibility. The HIGHT cipher consists of simple operations and provides adequate security level. The objective of this research work is to design, optimize, and model FPGA implementation of the HIGHT cipher. Several optimized designs are presented to minimize the required hardware resources and energy including the scalar and pipeline ones. Our analysis shows that the scalar designs have smaller area and power dissipation, whereas the pipeline designs have higher throughput and lower energy. Because of the fact that obtaining the best performance out of any implemented design mainly requires balancing the design area and energy, our experimental results demonstrate that it is possible to obtain such optimal performance using the pipeline design with two and four rounds per stage as well as with the scalar design with one and eight rounds. Comparing the best implementations of pipeline and scalar designs, the scalar design requires 18% less resources and 10% less power, while the pipeline design has 18 times higher throughput and 60% less energy consumption. Copyright © 2016 John Wiley & Sons, Ltd.

Cooperative communication is a technique that helps to improve the communication performance in wireless networks. It allows the nodes to rely on their neighbors when transmitting packets providing some diversity gain. Wireless sensor networks (WSNs) can benefit from cooperative communication to, which was proven by other researcher in the field. In this paper we consider security issues in WSNs with cooperative communications. We study such issues at each of the main protocol layers: physical layer, data link layer, network layer, services (topology) layer, and application layer. For each layer, we clarify the main task, enumerate the main attacks and threats, specify the primary security approaches and techniques, if any, and discuss possible new attacks and problems that may arise with the use of cooperative communications. Further, we showed for some attacks (e.g. jamming, packet dropping, and wormhole) that using cooperative communication improves the network resiliency and reliability. This paper builds the foundations and clarifies the specifications for a needed security protocol in WSNs with cooperative communications that can enhance its performance and resiliency against cyber-attacks.

ABSTRACT In wireless sensor networks (WSNs), sensor devices have limited supply of energy. The sensor death due to dissipating battery energy is one of the fundamental design issues in WSNs. Hence, energy efficiency is argued to be the most important requirement for any protocol designed for WSNs. With sensors acting as routers to transport the packets from a source to a destination sensor, multipath protocols are used to discover multiple paths with the objective to improve the reliability, efficiency, and security in WSNs. Selecting the path that minimizes the rate of sensors death and extends the lifetime of the network is the main challenge for multipath protocols. In this paper, we propose a new energy and security aware route selection (ESARS) protocol for WSNs. The first part of ESARS selects a route that maximizes the network lifetime based on a novel metric. The second part of ESARS finds the optimal security level for the selected path based on the estimated security risk of the path. Traditionally, these two parts are addressed separately in the literature, and this paper combines the two parts in one protocol. The proposed protocol is evaluated and compared with other protocols using both analytical analysis and extensive simulations. The results show that the proposed protocol not only achieves its main objective to extend the network lifetime by significantly reducing the sensors death rate but also uses the most optimal security level for the selected route. Moreover, in ESARS protocol, several threshold parameters were employed to provide flexibility per the needs of the application in which the sensors are used. Copyright © 2013 John Wiley & Sons, Ltd.

This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M processing elements (PEs), and provides a speedup of M compared with systems that use a single PE. An algorithm is provided to detect and resolve memory conflicts. A CMOS implementation of a four-PE processor is presented. The design is reconfigurable to compute various FFT sizes. The design power consumption is scalable based on the number of active PEs. The timing, area and power results are discussed.

This paper examines the use of a switch based architecture to implement a Radix-2 decimation in frequency fast Fourier transform engine. The architecture interconnects M processing elements with 2*M memories. An algorithm to detect and resolve memory access contention is presented. The implementation of 1024-point FFTs with 2 processing elements is discussed in detail, including timing and place-and-route results. The switch based architecture provides a factor of M speedup over a single processing element realization.

This paper examines the superscalar pipeline Fast Fourier Transform algorithm and architecture. The algorithm presents a memory management scheme to prevent memory contention throughout the pipeline stages. The fundamental algorithm, a switch-based FFT pipeline architecture and an example 64-point FFT pipeline are presented. The proposed superscalar architecture substantially improves the FFT processing. The pipeline consists of log2N stages, where N is number of FFT points. Each stage can have M Processing Elements (PEs.) As a result, the architecture speed up is M*log2N. The pipeline algorithm is configurable to any M ≫ 1.