EDBT 2026 Demo / reviewers in the wild / expert
Kirk Gould
dblp:18/4785
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 2Human-computer interaction and ubiquitous computing · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer graphics and multimedia
2 papers |
Rendering · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
GPUs and heterogeneous computing · 100% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
graphics accelerator |
0.0 | 2 | 1994 | A scalable hardware render accelerator using a modified scanline algorithm · SIGGRAPH 1992 Hardware accelerated rendering of CSG and transparency · SIGGRAPH 1994 |
Rendering › geometric rendering
constructive solid geometry rendering |
0.0 | 1 | 1994 | Hardware accelerated rendering of CSG and transparency · SIGGRAPH 1994 |
Rendering › surface rendering
transparency rendering |
0.0 | 1 | 1994 | Hardware accelerated rendering of CSG and transparency · SIGGRAPH 1994 |
Rendering › hidden surface removal
scan-line algorithms |
0.0 | 1 | 1992 | A scalable hardware render accelerator using a modified scanline algorithm · SIGGRAPH 1992 |
Methods — techniques the papers use, named apart from their topics
multiple-pass algorithm · 0.0image partitioning · 0.0front-to-back z-sorted shading · 0.0scalable architecture · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1994 | Hardware accelerated rendering of CSG and transparencyabstractThis paper describes algorithms for implementing accurate rendering of CSG and transparency in a hardware 3D accelerator. The algorithms are based on a hardware architecture which performs front-to-back Z-sorted shading; a multiple-pass algorithm which allows an unlimited number of Z-sorted object layers is also described. The multiple-pass algorithm has been combined with an image partitioning algorithm to improve efficiency, and to improve performance of the resulting hardware implementation. Michael Kelley, Kirk Gould, Brent Pease, Stephanie Winner, Alex Yen |
SIGGRAPH | 2 |
| 1992 | A scalable hardware render accelerator using a modified scanline algorithmabstractarticle Free Access Share on A scalable hardware render accelerator using a modified scanline algorithm Authors: Michael Kelley Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014 Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014View Profile , Stephanie Winner Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014 Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014View Profile , Kirk Gould Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014 Apple Computer, Inc., 20525 Mariani Avenue, Cupertino, CA 95014View Profile Authors Info & Claims ACM SIGGRAPH Computer GraphicsVolume 26Issue 2July 1992 pp 241–248https://doi.org/10.1145/142920.134069Online:01 July 1992Publication History 22citation718DownloadsMetricsTotal Citations22Total Downloads718Last 12 Months16Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF Michael Kelley, Stephanie Winner, Kirk Gould |
SIGGRAPH | 3 |