This paper presents an efficient, adaptive binary search (ABS) digital low dropout voltage regulator (LDO) for implantable medical devices (IMDs). The proposed regulator eliminates large overshoots associated with the conventional binary search while achieving a tracking speed better than the linear array regulators. The adaptive binary array starts with a 2-bit binary search, and the array size increases with higher load currents. The adaptive binary switch array operates within a digital frequency-locked loop (FLL), implemented using a differential voltage-controlled oscillator (VCO) and a fully digital frequency comparator. The proposed regulator is implemented in a 65 nm CMOS process and has a simulated output voltage of 0.8 V for a 0.24-52.3 mA load current range with a 1 V input. Working with a 1 V power supply, the regulator consumes a quiescent current of 11 µA.

This work presents a detailed quantitative analysis of the reference spurs in Charge Pump (CP) based multi-output Phase Locked Loops (PLL) caused by a current mismatch in the charge pump. Spur estimation is done using mathematical methods like Fourier series and Narrowband Frequency Modulation (NBFM) approximation. The basics of CP PLLs and the mechanism of reference spur generation are discussed. A behavioral model of a multi-output PLL with an integer-N loop and phase rotatory dividers is built using Verilog-AMS which generates two LO carriers of 1.352 GHz and 587 MHz. The model is simulated in Cadence and the results are post-processed in MATLAB. The simulation results match analytical results with an error of less than 1dBc/Hz.

This paper presents a wideband calibration-free compact mmWave transmitter (TX) with a high image rejection ratio (IMRR) for 5G applications. A novel architecture has been proposed using a double quadrature (DQ) direct upconversion modulator. The proposed TX architecture uses a 3-stacked differential power amplifier (PA) stage to increase Psat. New layout techniques have been proposed for the symmetric routing of quadrature LO signals. The TX designed in 40 nm CMOS process operates from 25-32 GHz. Post-layout EM simulations show 20 dBm of Psatat 28 GHz with 46.4 dB of IMRR. IMRR has been obtained ≥40 dB across the output bandwidth. The error vector magnitude (EVM) is better than -31 dB for a 256 QAM OFDM signal with 400 MHz signal bandwidth with an average output power of 9 dBm. An area-efficient implementation of mmWave TX delivering 20 dBm Psatis presented. The design also supports a wide IF bandwidth from 200 MHz to 1.5 GHz.

This paper presents a novel dual core inductive coupling based area efficient mm-Wave voltage controlled oscillator fabricated in 40 nm CMOS process for K-band applications. New inductive coupling techniques have been implemented for resonant mode switching between two VCO cores, each having an inductive divider based LC tank. Detailed mathematical analysis has been developed on the effect of various higher-order harmonics on waveform symmetry. Simulations are performed to explore the time-variance property of various noise-contributing elements in the VCO. The VCO fabricated in 40 nm CMOS process without an ultra-thick top metal layer occupies a core area of 0.065 mm2. The proposed layout floorplan reduces the active area requirement of multi-core VCO. The measured frequency tuning range is from 21.6 to 25.5 GHz. The proposed dual core VCO shows measured phase noise of -112 dBc/Hz and -115 dBc/Hz at 3 MHz and 10 MHz offset respectively for a center frequency of 22.5 GHz in 40 nm CMOS process. The VCO achieves a measured FoMT of 183 dBc/Hz at an offset of 3 MHz for a power consumption of 18.4 mA and a tuning range of$>$16$\%$demonstrating a practical solution.

This paper presents a low power mmWave Class-$\boldsymbol{\mathrm{F}_{234}}$voltage controlled oscillator (VCO) with a multi resonant Inductor-Capacitor (LC) tank. The proposed VCO designed in 40 nm CMOS technology, shows a 24.5 - 29.5 GHz continuous tuning. The VCO shows phase noise of -103 dBc/Hz and -116 dBc/Hz at 1 MHz and 10 MHz offset, respectively at 27.86 GHz while consuming 2.5 mW power at 0.5 V. FoMTof 186.7 dB has been obtained at 1 MHz offset. The tuning range is 18.5 % and the oscillator occupies 0.094 mm2.

This paper presents a baseband architecture consisting of a complex IQ bandpass filter followed by a 3-stage Variable Gain Amplifier (VGA) designed for multi-standard navigation receivers. A new dc offset correction circuit based on a low-pass feedback network is proposed for high gain VGA to cancel its own dc offset and that of the previous stage. The presented baseband circuits are incorporated into a multi-standard navigation receiver fabricated in 65 nm CMOS technology. The filter and VGA together provide a programmable gain of 43 dB over a tunable bandwidth of 2-4 MHz with less than 1-dB in-band attenuation. Occupying 0.39 mm2on-chip area, the filter and VGA draw a maximum current of 7 mA from a 1.2-V supply.

With the advent of miniaturised sensors for various engineering and medical applications there is an increased demand of low-power, low-voltage analog building blocks like opamps and OTAs. Degradation of certain amplifier characteristics with supply voltage is a major concern for low-voltage design and often poses contradictory requirement. CMRR (common mode rejection ratio), one such feature, is essential for sensing small bio-electric signals riding over large common-mode voltage. Here we focus on the challenging task of building a low-voltage OTA with high CMRR along with wide CMR (common mode range) and high output impedance. Robust tail current sources for a complementary differential pair OTA with folded cascode output is implemented for the purpose. The circuits are designed and simulated in 0.35 mum standard CMOS technology with supply voltage of 1.8 V. We could demonstrate a maximum of upto 40 dB increase in CMRR for a range of common-mode voltages.