This paper presents several corrections and comments to the above paper. Errors in the original very high speed integrated circuit hardware descriptive language (VHDL) code are identified. This paper also suggests much simpler optimized VHDL code to achieve the same result.

Wafer packing is a process of combining multiple chip designs on the same wafer such that the fabrication cost can be shared by several designs and hence reduced. This technique is widely used for designs that require a small number of dies or chips. It is essential to have computer algorithms to decide how to allocate designs to wafers in order to reduce the total fabrication cost. Based on different wafer fabrication techniques, two versions of the wafer packing problem are formulated. The authors study different variations for each version. They present algorithms to find optimal solutions for these variations which are polynomial-time solvable. They also present heuristic algorithms for those proven to be NP-hard. The effectiveness of the proposed algorithms is demonstrated by experimental results.>

The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets so that the number of vias is minimized. The problem is often referred to as the via minimization problem. The problem is considered for three-layer routing, concentrating on one version called the constrained via minimization (CVM3) problem. It is shown that the CVM3 problem is NP-complete and a heuristic algorithm is proposed. The experimental results show that the proposed algorithm is efficient and generates fairly good solutions.>

The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets. The objective of the layer assignment problem in general is to minimize the number of vias required. Thus, it is also referred to as the via minimization problem. In a via minimization problem, if the topology of the given layout is fixed, the problem is referred to as a constrained via minimization (CVM) problem. On the other hand, if both the topology of the layout and the layer assignment are to be decided, it is referred to as an unconstrained via minimization (UVM) problem. In this paper, both the CVM and UVM problems are studied. For the CVM problems, efficient algorithms which can be easily modified to take extra constraints into consideration are proposed. Experimental results show that the proposed algorithms for the CVM problem are time efficient compared with existing algorithms and generate better (near-optimal) results. For the UVM problems, a new heuristic approach is presented which generates better results but takes longer computing time. In the CVM problem, some vias are "essential" to the given layout. That is, they have to be selected and cannot be replaced by other possible vias. An efficient algorithm for identifying essential vias is also presented and discussed in this paper.

The objective of the via minimization is to assign wire segments into different layers to minimize the number of vias required. Several algorithms have been proposed for the Constrained Via Minimization (CVM) problem where the topology of the given layout is fixed. In a CVM problem, some vias may be “essential” to the given layout. That is, they have to be selected and cannot be replaced by other vias. In this paper we present a procedure to find most of the essential vias. This procedure can be used as a preprocessor for the algorithms for CVM problems. Experimental results show that the procedure is efficient and can identify most of essential vias.

The routing problem for Printed-Circuit Boards (PCB's) is crucial in the fabrication of today's digital systems. Traditionally, this problem has been divided into two main sub-problems: layer assignment and routing. Considering these two problems apart from each other may cause uneven wire distribution both among the wiring layers and within each layer. Uneven wire distribution among the wiring layers could increase the number of wiring surfaces required for the routing. Uneven wire distribution within a layer could result in an unfeasible routing. We propose a new approach to deal with the routing of PCB's in technologies which allow short vias. The proposed methodology considers the layer assignment and routing problems in a unified fashion. Based on some global information, our algorithm first estimates the initial number of layers required for the routing. It then determines an ordering in which nets should be considered during the layer assignment process. The results of our experiments show that our algorithm is of practical use.