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Lakshmi N. Goyal

dblp:18/5164 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1976
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorTheory of computation · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 56% Processor architecture and microarchitecture · 44%
Theoretical computer science
1 paper
Algorithms and data structures · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
arithmetic unit		 0.011976
A Note on Atrubin's Real-Time Iterative Multiplier · IEEE Trans. Computers 1976
Integrated circuit design › digital arithmetic circuits
iterative multiplier		 0.011976
A Note on Atrubin's Real-Time Iterative Multiplier · IEEE Trans. Computers 1976
Algorithms and data structures
computer arithmetic		 0.011976
A Note on Atrubin's Real-Time Iterative Multiplier · IEEE Trans. Computers 1976
Integrated circuit design › digital circuit design › logic array
cellular array design		 0.011976
A Note on Atrubin's Real-Time Iterative Multiplier · IEEE Trans. Computers 1976

Methods — techniques the papers use, named apart from their topics

real-time iterative multiplication · 0.0
YearPublicationVenuePosition
1976 A Note on Atrubin's Real-Time Iterative Multiplier
abstract
This correspondence presents a new multiplication algorithm for Atrubin's one-dimensional real-time iterative multiplier such that all the cells including the first cell in the array are identical in all respects, for the no-delay case.
Lakshmi N. Goyal
 IEEE Trans. Computers1
1975 Design of an arithmetic element for serial processing in an iterative structure
abstract
This paper describes the arithmetic and logic design of the digit processing logic of an arithmetic element. The arithmetic element is used in an iterative structure and arithmetic processing takes place serially on a digit by digit basis with the most significant digit first. Starting from the arithmetic specification of the digit processing logic, the arithmetic design (namely, the choice of number system, number representation and the digit algorithm) is developed. Algebraic and logic designs of the logic necessary to execute the digit algorithm and its implication for LSI implementation are discussed.
Lakshmi N. Goyal
 IEEE Symposium on Computer Arithmetic1