EDBT 2026 Demo / reviewers in the wild / expert
Pedro Diaz
dblp:18/5597
· DBLP profile ↗
4ranked-venue papers
1as first author
0since 2021 · last 2012
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-authorArtificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 76% Processor architecture and microarchitecture · 24% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache coherence |
0.1 | 1 | 2011 | Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters · IEEE Trans. Computers 2011 |
Memory systems › cache coherence
software cache coherence |
0.1 | 1 | 2011 | Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters · IEEE Trans. Computers 2011 |
Memory systems
cache |
0.1 | 1 | 2009 | Stream chaining: exploiting multiple levels of correlation in data prefetching · ISCA 2009 |
Memory systems › cache › prefetching
data prefetching |
0.1 | 1 | 2009 | Stream chaining: exploiting multiple levels of correlation in data prefetching · ISCA 2009 |
Memory systems › memory access optimization
stream-based prefetching |
0.1 | 1 | 2009 | Stream chaining: exploiting multiple levels of correlation in data prefetching · ISCA 2009 |
Processor architecture and microarchitecture
chip multiprocessor |
0.0 | 1 | 2011 | Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters · IEEE Trans. Computers 2011 |
Processor architecture and microarchitecture
multicore design |
0.0 | 1 | 2011 | Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters · IEEE Trans. Computers 2011 |
Methods — techniques the papers use, named apart from their topics
self-invalidation · 0.1forced writeback · 0.1bloom filter · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2012 | Optimizing H.264/AVC interprediction on a GPU-based frameworkabstractSUMMARY H.264/MPEG‐4 part 10 is the latest standard for video compression and promises a significant advance in terms of quality and distortion compared with the commercial standards currently most in use such as MPEG‐2 or MPEG‐4. To achieve this better performance, H.264 adopts a large number of new/improved compression techniques compared with previous standards, albeit at the expense of higher computational complexity. In addition, in recent years new hardware accelerators have emerged, such as graphics processing units (GPUs), which provide a new opportunity to reduce complexity for a large variety of algorithms. However, current GPUs suffer from higher power consumption requirements because of its design. Up to now, GPU‐based software developers have not taken this into account. In this paper, we present a detailed procedure to implement the H.264 motion estimation for a GPU, with the aim of reducing time and, as a consequence, the energy consumption. The results show a negligible drop in rate distortion with a time reduction of over 91.5% on average and it reduces the energy consumption by a factor of 11.78 compared with the reference implementation. Copyright © 2011 John Wiley & Sons, Ltd. Rafael Rodríguez-Sánchez 0001, José Luis Martínez 0001, Gerardo Fernández-Escribano, José L. Sánchez 0002, José M. Claver, Pedro Diaz |
Concurr. Comput. Pract. Exp. | 6 |
| 2011 | Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom FiltersabstractImplementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing coherence protocols in hardware, an approach with some design complexity, hardware costs, and restrictions on interconnect behavior. However, for some memory consistency models, an alternative is to enforce coherence in the software implementation of synchronization primitives, using software controlled invalidations and forced writebacks. This requires minimal hardware support but gives less selective enforcement, which affects performance. This paper proposes a novel hybrid software-hardware coherence mechanism. In this scheme, software is responsible for triggering the coherence actions-self-invalidations and writebacks-at appropriate times while hardware uses Bloom filters to perform more selective self-invalidations. We evaluate the proposed scheme on applications from two different domains: the SPLASH-2 scientific and ALP multimedia benchmarks. Experimental results show that while the software-only coherence scheme shows less performance degradation than expected, it still unacceptably degrades performance for some of the benchmarks. Filtering out unnecessary invalidations improves the worst-case performance by as much as 93 percent, and brings the performance of the hybrid scheme within five percent of full hardware coherence for 10 out of 13 benchmarks, on a 32-core CMP with a shared L2 cache. Thomas J. Ashby, Pedro Diaz, Marcelo Cintra |
IEEE Trans. Computers | 2 |
| 2009 | Stream chaining: exploiting multiple levels of correlation in data prefetchingabstractData prefetching has long been an important technique to amortize the effects of the memory wall, and is likely to remain so in the current era of multi-core systems. Most prefetchers operate by identifying patterns and correlations in the miss address stream. Separating streams according to the memory access instruction that generates the misses is an effective way of filtering out spurious addresses from predictable streams. On the other hand, by localizing streams based on the memory access instructions, such prefetchers both lose the complete time sequence information of misses and can only issue prefetches for a single memory access instruction at a time. Pedro Diaz, Marcelo Cintra |
ISCA | 1 |
| 1995 | Manipulation of Volume and Graphics Objects for the Visualization of Medical Data under OpenGL (tm)abstractCombined rendering of volume data and geometric objects (graphics objects) is important in a number of medical applications. Efficient generation of such rendering is required to support user interactions at a level that are useful in clinical applications. In this study, we describe the manipulation of graphics objects with volume data utilizing a widely used graphics API standard, OpenGL.> Zhenghong Lee, Pedro Diaz, Errol Bellon |
CBMS | 2 |