Lightweight Temporal Compression (LTC) is among the lossy stream compression methods that provide the highest compression rate for the lowest CPU and memory consumption. As such, it is well suited to compress data streams in energy-constrained systems such as connected objects. The current formulation of LTC, however, is one-dimensional while data acquired in connected objects is often multi-dimensional: for instance, accelerometers and gyroscopes usually measure variables along 3 directions. In this paper, we investigate the extension of LTC to higher dimensions. First, we provide a formulation of the algorithm in an arbitrary vectorial space of dimension n. Then, we implement the algorithm for the infinity and Euclidean norms, in spaces of dimension 2D+t and 3D+t. We evaluate our implementation on 3D acceleration streams of human activities. Results show that the 3D implementation of LTC can save up to 20% in energy consumption for low-paced activities, with a memory usage of about 100 B.

The orientation estimation filter proposed by Madgwick [1] for inertial and inertial/magnetic sensors have been successfully used as a core solution in a variety of commercial low-power motion tracking devices. The approach offers a high accuracy and reduces the computational cost compared to the state-of-the-art Kalman-based methods [10]. In this paper, we propose a modification to the Gradient Descent correction step in [1], which guarantees the improvement of accuracy in quaternion estimation without increasing the total number of required scalar arithmetic operations. Monte Carlo simulations with typical statistical characteristics for sensor errors have shown an average 37.2% improvement in dynamic root-mean-square error of Euler angles.

Accelerometers are vital parts of many industrial and biomedical applications. Such applications have high demands for accuracy. Multi-sensor fusion is an efficient approach to deliver accurate sensor readouts that are tolerant to multiple faults. This paper proposes an efficient data fusion algorithm, which minimizes Mean-Square-Error (MSE) and keeps the overall precision of the system high. We make use of a convex optimization scheme to tackle the problem. Furthermore, a pre-processing step called screening is used to exclude the potentially faulty sensors from the data fusion. The screening process makes it possible to quickly detect multiple faulty sensors. Our data fusion approach is applicable to any multi-sensor system, for which the post-calibration statistical characteristics of sensors can be measured experimentally. However, the results are presented for accelerometers.

Sensor data fusion is a common approach to provide accurate and fault-tolerant sensor readouts in a multisensor system. This paper proposes an efficient data fusion algorithm using convex optimization for a multi-sensor system with given post-calibration statistical characteristics. A preprocessing step called screening is proposed to quickly detect multiple faulty sensors and exclude them from the fusion. Experimental results are evaluated on temperature sensors.

Fixed-point accuracy analysis and optimization of polynomial data-flow graphs with respect to a reference model is a challenging task in many digital signal processing applications. Range and precision analysis are two important steps of this process to assign suitable integer and fractional bit-widths to the fixed-point variables and constant coefficients in a design such that no overflow occurs and a given error bound on maximum mismatch (MM) or mean-square-error (MSE) and signal-to-quantization-noise ratio (SQNR) is satisfied. This paper explores efficient optimization algorithms based on robust analyses of MM and MSE/SQNR for fixed-point polynomial data-flow graphs. Experimental results illustrate the robustness of our analyses and the efficiency of the optimization algorithms compared to previous work.

Fixed-point accuracy analysis of imprecise datapaths in terms of Maximum-Mismatch (MM) [1], or Mean-Square-Error (MSE) [14], w.r.t. a reference model is a challenging task. Typically, arithmetic circuits are represented with polynomials; however, for a variety of functions, including trigonometric, hyperbolic, logarithm, exponential, square root and division, Coordinate Rotation Digital Computer (CORDIC) units can result in more efficient implementations with better accuracy. This paper presents a novel approach to robustly analyze the fixed-point accuracy of an imprecise datapath, which may consist of a combination of polynomials and CORDIC units. The approach builds a global polynomial for the error of the whole datapath by converting the CORDIC units and their errors into the lowest possible order Taylor series. The previous work for almost accurate analysis of MM [1] and MSE [14, 15] in large datapaths can only handle polynomial computations.

Multi-sensor data fusion is an efficient method to provide both accurate and fault-tolerant sensor readouts. Furthermore, detection of faults in a reasonably short amount of time is crucial for applications dealing with high risks. In order to deliver high accuracies for the sensor measurements, it is required to perform a calibration for each sensor. This paper focuses on designing a fault-tolerant calibrated multisensor system. First, the least squares method is applied to calibrate each sensor using a linear curve fitting function. Next, an analytical technique is proposed to carry out a fault-tolerant multi-sensor data fusion, while minimizing the Mean-Square-Error (MSE) for the final sensor readout. While our data fusion approach is applicable to different multi-sensor systems, the experimental results are shown for 16 temperature sensors, where an environmental thermal chamber was used as the reference model to calibrate the sensors and perform the measurements.

Arithmetic Transform (AT) [1, 16, 17] is an efficient spectral technique, to analyze range and precision of fixed-point polynomial datapaths, among other methods including AA [4, 15] and SMT [5]. However, the major inefficiency of AT is that it cannot handle the datapaths with comparator units, which imply the non-arithmetic if-statements. This paper presents the approach, Constrained Arithmetic Transform (CAT), to perform range and precision analysis of fixed-point datapaths with comparator units. A custom branch-and-bound search is also introduced to provide more cutting branches and perform faster analyses of range and precision, by making use of safe and negligible overestimations. Experimental results prove the efficiency of our approach.

Analyses of range and precision are important for high-level synthesis and verification of fixed-point circuits. Conventional range and precision analysis methods mostly focus on combinational arithmetic circuits and suffer from major inefficiencies when dealing with sequential linear-time-invariant circuits. Such problems mainly include inability to analyze precision when quantization of constant coefficients is taken into account, and lacking efficient word-length optimization algorithms to handle both variables and constants, while satisfying the error metrics. The algorithms presented in this paper solve these problems. Experiments illustrate the efficiency and robustness of our algorithms.

Fixed-point Fast Fourier Transform (FFT) units are widely used in digital communication systems. The twiddle multipliers required for realizing large FFTs are typically implemented with the Coordinate Rotation Digital Computer (CORDIC) algorithm to restrict memory requirements. Recent approaches aiming to optimize the bit-widths of FFT units while satisfying a given maximum bound on Mean-Square-Error (MSE) mostly focus on the architectures with integer multipliers. They ignore the quantization error of coefficients, disabling them to analyze the exact error defined as the difference between the fixed-point circuit and the reference floating-point model. This paper presents an efficient analysis of MSE as well as an optimization algorithm for CORDIC-based FFT units, which is applicable to other Linear-Time-Invariant (LTI) circuits as well.

Range and precision analysis are important steps in assigning suitable integer and fractional bit-widths to the fixed-point variables in a design such that no overflow occurs and a given error bound on maximum mismatch and (or) Mean-Square-Error (MSE) is satisfied. Although, range and maximum mismatch analysis of linear arithmetic circuits has been studied before [8], regarding analysis of MSE, the previous works [9,10,12] cannot analyze the error, when it is defined as the difference between the fixed-point circuit and the reference model, e.g., floating-point format. This paper presents an efficient analysis of MSE for linear arithmetic circuits narrowing on Fast Fourier Transform (FFT) units. Furthermore, an optimization algorithm is introduced to set the bit-widths in an FFT unit while satisfying a given maximum bound on MSE. Experimental results prove the robustness of our MSE analysis and the efficiency of the optimization algorithm compared to [12] for an 8K FFT unit.

This paper presents a new technique for scaling the intermediate variables in implementing fixed-point polynomial-based arithmetic circuits. Analysis of precision has been used first to set the input and coefficient bit-widths of the polynomial so that a given error bound is satisfied. Then, we present an efficient approach to scale and truncate different intermediate variables with no need of re-computing precision at each stage. After applying it to all the intermediate variables, a final precision computation and sensitivity analysis is performed to set the final values of truncation bits so that the given error bound remains satisfied. Experimental results on a set of polynomial benchmarks show the robustness and efficiency of the proposed technique.

This paper presents several efficient architectures of dynamic/static edge-triggered flip-flops with a compact embedded logic. The proposed structure, which benefits from the overlap period, fixes most of the drawbacks of the dynamic logic family. The design issues of setting the appropriate overlap period for this architecture are explained. The proposed overlap-based approach is compared with several state-of-the-art dynamic/static logic styles in implementing a 4-bit shift register and an odd-even sort coprocessor using different CMOS technologies. The simulation results showed that the overlap-based logic cells become much more efficient when the complexity of their embedded logic function increases. Moreover, this approach improves static power consumption, which makes it even more efficient in below 0.18 ¿m CMOS technologies.

Datapath designs that perform polynomial computations over Z 2 nare used in many applications such as computer graphics and digital signal processing domains. As the market of such applications continues to grow, improvements in high-level synthesis and optimization techniques for multivariate polynomials have become really challenging. This paper presents an efficient algorithm for optimizing the implementation of a multivariate polynomial over Z 2 n in terms of the number of multipliers and adders. This approach makes use of promising heuristics to extract more complex common sub-expressions from the polynomial compared to the conventional methods. The proposed algorithm also utilizes a canonical decision diagram, Horner-Expansion Diagram (HED) [1] to reduce the polynomial's degree over Z 2 n. Experimental results have shown an average saving of 27% and 10% in terms of the number of logic gates and critical path delay respectively compared to existing high-level synthesis tools as well as state of the art algebraic approaches.

Integer multipliers with finite output bit-widths are widely used in many Digital Signal Processing (DSP) applications. In such circuits high-level optimizations like Residue Number System (RNS) can be utilized to achieve more efficient architectures compared to the conventional binary representations. This paper presents an efficient high-level Don't-Care Optimization (DC-Opt) method for integer multipliers and in general Multiply Accumulator (MAC) units when the output result is limited to a finite bit-width. This high-level optimization approach can then be combined with logic optimizations at gate-level. Experimental results have shown major improvements in terms of area and latency compared to the conventional optimization approaches.

This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, XOR extraction, and carry-signal mapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted XORs into half/full-adders to make a very fast debugging algorithm. This approach is robust under multioperand adders, pin-swap techniques, optimizations concerning carry signals or XOR terms, and irregularities, such as commutative and associative laws. Moreover, the XOR extraction in the proposed algorithm is much faster than conventional techniques, as it does not evaluate the whole netlist. The bugs detected in the partial product initialization and the carry-signal mapping can automatically be replaced with proper logics. However, during the XOR extraction phase, the problematic XORs are only reported by the algorithm, and no automatic replacement is performed for such logic gates. To evaluate the effectiveness of our approach, we run it on several arithmetic circuits.

In this paper, we propose a novel approach to extract a network of half adders from the gate-level net-list of an addition circuit while no internal equivalences exist. The technique begins with a gate-level net-list and tries to map it into word-level adders based on an efficient bit-level adder representation. It will be shown that the proposed technique is suitable for several gate-level architectures of multipliers, as it extracts adder components in a step-wise method. This approach can also be generalized to other arithmetic circuits. In order to evaluate the effectiveness of our approach, we run it on several arithmetic circuits and compare experimental results with those of contemporary techniques.

Clock overlap is an important issue in the design of sequential circuits and is typically avoided. In this paper we present a new power-efficient edge-triggered D flip-flop in which we have benefited from the overlap period of the clock signal. The design procedure of the proposed D flip-flop is presented. The performance of the flip-flop is compared with several state of the art flip-flops in a shift register and a pipeline adder in 0.18μm CMOS technology. The proposed flip-flop has the lowest power-delay-product and consumes less area compared to others.