High performance circuits are facing increasingly severe signal integrity problems due to crosstalk noise and crosstalk noise awareness has become an integral part of static timing analysis (STA). Existing crosstalk noise aware STA methods compute noise induced delay uncertainty on a net by net basis and in a pessimistic way, without considering the overlap bounds of the victim and aggressor timing windows and realistic delay impact on early and late signal arrival times. Since crosstalk induced delay on individual nets contribute cumulatively on data and clock paths, even small amounts of pessimism in computation can add up to produce several unrealistic timing violations. Unlike glitch noise analysis where noise often attenuates during propagation, quality of delay noise analysis is severely affected by any pessimism in noise estimation and can unnecessarily cost valuable silicon and design resources for fixing unreal violations. In this paper, we propose two temporal techniques to reduce pessimism in crosstalk noise aware STA. The first method, "effective delay noise", is a net based method where the exact overlap points of victim and aggressor timing windows are considered to obtain the part of delay noise that actually impacts early and late signal arrival times. The second method, "path based delay noise", is a path based method where the reduced arrival uncertainty of the nets of a given path are utilized for pessimism reduction. We also propose a novel "uncertainty propagation" technique as part of the second method, which results in an iteration free crosstalk noise aware STA of the path with significantly reduced pessimism. The two techniques are combined in a proposed methodology that is compatible with existing industrial static timing analyzers with very little computational overhead compared to the traditional noise aware STA and a significant improvement in eliminating unreal violations. The proposed techniques resulted in 77% reduction of worst case negative slack and 57% reduction in the number of failing paths in the setup analysis of a 90nm industrial design.

Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that, by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic postroute gate-sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high-performance designs.

Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic post-route gate sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high performance designs.