Memory allocation efficiency remains a significant challenge in High-Level Synthesis (HLS) frameworks. Current dynamic memory management (DMM) techniques suffer from issues such as inefficiency, fragmentation, considerable hardware overhead, and difficulties in handling complex workloads. Conversely, existing static memory approaches often exhibit poor efficiency when addressing large-scale applications. Moreover, both dynamic and static methods lack sufficient support for High Bandwidth Memory (HBM), thereby limiting their effectiveness in complex neural network scenarios. To overcome these challenges, we propose an optimized static memory allocation strategy specifically designed for FPGA systems. Our approach leverages the computational characteristic of neural network applications, which typically exhibit cyclic and fixed-bound behaviors. We tightly integrate an MLIR-based compiler with an efficient static memory allocator, eliminating the need for dedicated allocator hardware while ensuring efficient runtime memory access. Furthermore, we introduce a customized AXI bus distribution mechanism and an address mapping strategy optimized for the multi-port and multi-bank architecture of HBM. This design significantly enhances bandwidth utilization and reduces latency. Experimental results confirm that our proposed methodology substantially improves allocation efficiency, spatial utilization, and effectively manages complex memory scenarios, thereby outperforming existing state-of-the-art solutions.

Multi-corner timing analysis is essential for ensuring the robustness of circuits under variations in process, voltage, and temperature (PVT). Along with clock skew scheduling, delay padding is used to address hold violations. However, applying padding consistently in multiple corners is challenging due to conflicting constraints and the prevalence of “ping-pong” effects. This paper presents a novel methodology that uses dual decomposition to tackle this challenge. The problem is divided into a set of network flow problems, one for each corner. These problems are coupled through shared delay variables. Coordinating these subproblems using Lagrange multipliers ensures consistent padding assignments across corners. Additionally, traditional padding methods often struggle with physical feasibility. The incorporation of path relationship analysis is proposed to identify viable, physically feasible padding locations. Experimental results on industrial benchmarks demonstrate that the proposed method efficiently identifies feasible padding solutions and achieves the minimum clock period that satisfies the setup and hold time constraints for all corners. Compared to the single worst-case corner baseline, the optimized clock period is reduced by up to 9%, highlighting the effectiveness of our approach.

Traditional FPGA PLB designs are constrained by the exponential increase in LUT area with the augmentation of inputs. Recent work has explored a pruned LUT based on the non-uniform distribution of Boolean functions in practical benchmarks, designing an 8-input PLB with enhanced functionality and a modest area overhead. Nonetheless, the existing LUT pruning algorithm is prone to local optima and focuses exclusively on SRAM pruning, neglecting lookahead optimization of the MUX tree. In this paper, we propose Compacted-LUT (CLUT), a fine-grained customizable LUT architecture via SRAM-MUX co-optimization. Based on the principle of LUT pruning, we design a novel representation for Boolean functions. This representation directly associates each Boolean function with the number of required SRAMs and MUX-tree transistors. On this basis, a novel evaluation model for the hardware-friendliness of Boolean functions can be formulated. We further design a beam search algorithm to identify an optimal subset of Boolean functions in target benchmarks based on evaluation results. With this subset, the customizable SRAM-MUX co-optimized CLUT architecture can be generated. Furthermore, we propose Asym-CLUT6, a function-diverse 8-input PLB composed of two variant 6-input CLUTs. We evaluate Asym-CLUT6 on VTR and Koios benchmarks. Post-route results show that, compared to the Altera Stratix 10-like architecture and Dual-RLUT6, Asym-CLUT6 reduces the area-delay product by 13.65% and 10.06% on average.

High-level synthesis (HLS) tools have drawn considerable attention in recent years because they can automatically generate hardware description code from high-level semantics under compiler-controlled configurations. However, the time-consuming design process, the inherent trade-offs among design objectives, and the often suboptimal quality of RTL produced by HLS have meant that prior studies rarely scale to or investigate the downstream stages beyond HLS.In this paper, we present COLA, an end to end design space exploration (DSE) framework that effectively automates the adaptive tuning of compiler transformation sequences and logic synthesis directives. First, we introduce MOEBO, a holistic Bayesian optimization method that builds multiple local surrogate models within trust regions while maintaining a global surrogate to correct local search bias and align decisions across regions. We further design a cooperative acquisition maximization scheme that coordinates these surrogates to propose diverse and promising candidates in parallel. Additionally, we employ reinforcement learning (RL) techniques to optimize logic synthesis by exploring the design space more effectively, improving the quality of the generated RTL and minimizing the area-delay product. The RL model dynamically adapts the logic synthesis directives to achieve better optimization outcomes over traditional methods. Experimental results show that, our framework achieves a substantial speedup across diverse accelerators for varying kernel granularities with a better trade-off between area and performance.

Coarse-grained Reconfigurable Architecture (CGRA) is a competitive accelerator architecture for computation-intensive loop kernels. Spatial CGRA is a typical CGRA that performs all the operations spatially to reduce reconfiguration costs within a single iteration, demanding high data parallelism. To achieve this goal, one of the main challenges is the loop-carried dependency between memory accesses. Many existing CGRA compilers struggle to precisely analyze the dependency distance, especially when accesses involve complex address patterns. Consequently, these compilers often default to setting the distance to one, based on a worst-case assumption, leading to degraded performance. However, we observe that a precise distance can improve performance significantly, raising the requirement for an efficient distance calculation approach. Another challenge is the performance constraints of single-bank memory, which necessitate the designer partitioning the original data into a multi-bank memory. However, we observe that the mapping result can cause the inter-iteration conflict, thereby invalidating the memory partition scheme. Therefore, an efficient post-mapping conflict detection is required. In this paper, we develop a constraint satisfaction problem (CSP)-based approach for calculating dependency distance and detecting conflicts, which determines the maximum available dependency distance and identifies conflicts within both intra- and inter-iterations. Besides, we formulate access scheduling as a graph coloring problem, which can minimize conflicts and improve performance. Overall, we develop a comprehensive end-to-end framework with architectural and compiler support for efficient data parallelism on spatial CGRA. We conduct extensive experiments to systematically evaluate the impact of different approaches on performance and compilation. Evaluation results show that our architecture can achieve 13.16× and 1.19× (up to 1.68×) average performance improvements compared to a RISC-V CPU and a state-of-the-art CGRA SoC, respectively. Besides, our architecture has 7.38× and 1.18× (up to 1.65×) average energy efficiency gains compared to these two architectures.

As the size of a circuit increases, previous reinforcement learning (RL) approaches struggle to effectively explore the logic optimization sequences of large-scale Boolean networks due to the long runtime overhead with poor optimization results. This article proposes LOFMPL: an open-source logic optimization framework with Maximum Fanout-Free Cone (MFFC) based hypergraph partitioning and reinforcement learning. The novel two-stage MFFC-based hypergraph partitioning can divide the circuit into highly independent subnetworks, which can be explored by an enhanced parallel RL-based design space exploration engine with an improved objective function. The experiment is conducted based on more than 150 benchmarks with logic optimization and ASIC technology mapping tasks and compared with other ML-based and greedy methods. The different partitioning algorithms are also compared for the subsequent logic optimization. Experimental results demonstrate that the proposed partitioning algorithm significantly enhances optimization quality without greatly increasing partitioning time, outperforming the KaHypar algorithm. Additionally, for the logic optimization task, the proposed method achieves a node-level-product improvement of 13% over the RLG synthesis exploration technique, 3% over the ESE reinforcement learning framework, 14% over the Boils synthesis method, and 7% over the DRiLLS synthesis method, while delivering greater reductions in node count compared with the Bulls-Eye optimization technique. For the ASIC technology mapping task, the proposed method achieves an area-delay-product improvement of 23% over the LSOracle framework, 9% over the Boils synthesis method, and 5% over the DRiLLS synthesis method. Hence, LOFMPL can achieve better results within the same runtime constraints compared with state-of-the-art works.

The rapid progress of artificial intelligence (AI) has brought increasing demands on hardware accelerators, particularly as modern models combine dense linear operations with a growing number of irregular, nonlinear, and control-intensive operators. While tensor cores and systolic arrays offer high throughput for regular computations, they often struggle to efficiently support the diverse operations emerging in recent model structures. Coarse-grained reconfigurable arrays (CGRAs), with their spatial parallelism and reconfigurability, may serve as a natural complement to dense accelerators in such heterogeneous workloads. In this work, we propose EUREKA, a heterogeneous acceleration framework that integrates tensor cores with CGRAs through a unified instruction set, cross-architecture data scheduling, tailored hardware support for nonlinear operators, and optimizations at the instruction, task, and operator levels to exploit parallelism. At the software level, we introduce a hierarchical compilation strategy that combines graph-level optimizations with tensor-level scheduling techniques. To address the large design space of hardware–software co-optimization, we further develop a Bayesian optimization-based exploration scheme enhanced with kernel compression methods, which provides an efficient means of identifying promising hardware configurations and scheduling strategies. Experiment results on representative AI benchmarks show that EUREKA improves execution efficiency, achieving an average$12.6\times $normalized performance gain over state-of-the-art frameworks.

Coarse-Grained Reconfigurable Architecture (CGRA) is a competitive accelerator architecture for computation-intensive loop kernels. Spatial CGRA is a typical CGRA that performs all the operations spatially, demanding high data parallelism. Given the performance limitations of single-bank memory, partitioning original data into multi-bank memory within the spatial CGRA is favored. However, we observe that the mapping result can cause the inter-iteration conflict, thereby invalidating the memory partition scheme.

Clock skew scheduling is a cost-effective technique for enhancing the synchronous digital VLSI systems. The technique solely requires adjusting the clock skew to meet the timing constraints of the signal paths in order to increase the clock frequency or yield. In the past, Gaussian distributions were commonly assumed in the probability density function (PDF) modeling of maximum and minimum path delays under process variations. However, this assumption may not be appropriate due to the notable asymmetry of the actual path delay distributions. In this paper, we suggest the generalized extreme value (GEV) distribution as a potential alternative. Furthermore, we evaluate maximum likelihood estimation, linear-moments, and the method of moments (MoM) for parameter estimation. Experimental results show that the GEV distribution can more accurately approximate the cumulative distribution function (CDF) of the benchmark circuit path delays, resulting in an average improvement of 40% in the Kolmogorov-Smirnov (KS) statistic. Furthermore, yield-driven clock skew scheduling based on the GEV distribution produces superior timing yield outcomes compared to that based on the Gaussian distribution, with an improvement in timing yield up to 33% and average 8%.

Designing processor microarchitectures is increasingly challenging due to a vast design space and the need to balance multiple metrics. Traditional algorithm-driven design space exploration (DSE) approaches often struggle to incorporate the extensive domain knowledge of expert architects. To address this, we introduce LEMOE, a multi-objective microarchitecture optimization framework that leverages large language model (LLM) to enhance an implicit Bayesian model. LEMOE features a program-aware warm-up phase utilizing LLM and LLVM to produce an initial design set with rich prior knowledge. By harnessing LLM’s contextual learning, our approach improves surrogate modeling and sampling under sparse data conditions. Experiment results show that LEMOE achieves a $22.8 \%$ improvement in energy efficiency with the same number of iterations and a $2.9 \times$ runtime speedup for the same target compared to prior works.

To fully harness emerging computing architectures, compilers must provide intuitive input handling alongside powerful code optimization to unlock maximum performance. Coarse-Grained Reconfigurable Arrays (CGRAs) — highly energy-efficient for nested-loop applications — have lacked a compiler capable of meeting these objectives. This paper introduces the Adora compiler [1], which effectively bridges user-friendly, lightweight coding inputs with high-performance acceleration on the CGRA SoC. Adora utilizes CGRA-target loop transformations to achieve efficient data-flow level execution while optimizing data communication and task pipelining at the task-flow level. Additionally, it incorporates a comprehensive automated algorithm with a thoughtfully designed optimization sequence. A series of comprehensive experiments highlights the exceptional efficiency and scalability of the Adora compiler, demonstrating its transformative impact in leveraging CGRA capabilities for acceleration in edge computing.

Transistor-level design is pivotal for the accurate evaluation of FPGA architectures. Since traditional linear models are increasingly inadequate in advanced technology nodes, simulation-driven approaches have become the standard for FPGA architecture exploration. However, due to the non-analytical nature of delay measurements from simulations, the transistor sizing process becomes a black-box optimization problem. COFFE2 [1], [2], the state-of-the-art academic sizing tool employs a division-based brute-force approach, which is relatively time-consuming and may lose optimal solutions. In this paper, we propose a two-phase transistor sizing methodology and enhance the COFFE2 framework with Bayesian Optimization, which is well-suited for black-box optimization problems. Our proposed approach not only achieves a 11.7% improvement in the quality of results but also reduces runtime by ~40%-70%. Through extensive benchmarking on a complete design flow, from transistor-level sizing to routing with VTR benchmarks, we demonstrate that FPGA architectures optimized by our approach offer an 11.0% reduction in the area-delay product, proving the efficacy of our method.

Look-up table (LUT)-based programmable logic blocks (PLBs) serve as the foundation for FPGAs. As increasing the input number of LUTs to improve logic capacity will introduce exponential area overhead, substantial research has focused on designing more efficient alternatives. Previous approaches primarily design dedicated hardware by analyzing the distribution of Boolean functions and implementing those with high frequency. However, these approaches face scalability challenges due to the explosive growth in the function space. In this paper, we consider the topology of cuts rather than Boolean functions they represent. By identifying topologies that occur commonly in cuts and integrating them with LUTs, we propose a new 8-input PLB architecture, named FLAIC. This architecture incurs only a slight area overhead compared to a 6-LUT while achieving logic capacity comparable to that of an 8LUT. Post-synthesis results demonstrate that FLAIC reduces the logic levels by over 20 % and the number of PLBs by more than$\mathbf{1 0 \%}$, compared to 6-LUTs. Additionally, post-implementation results show improvement in critical path delay by 10.6 % and a reduction in the number of Configurable Logic Blocks (CLBs) by 5.3 % on MCNC and VTR benchmarks, compared to the Intel Stratix 10-like architecture.

The routing architecture significantly impacts the performance of modern FPGAs, motivating extensive research into its design space exploration (DSE). However, DSE efficiency is hindered by non-generalizable parametrization methods and considerable runtime overhead of FPGA architecture evaluation tools. In this paper, we propose GEF, a GNN-based FPGA Evaluation Framework that predicts routability and area-delay product (ADP) across various routing architectures. In GEF, we introduce Intra-Tile Graph, a novel intermediate representation (IR) that encodes global routing patterns in a compact form, serving as the input to predictors. The Routability Predictor (Rou-P) integrates Self-Attention Pooling (SAGPool), while the ADP Predictor (ADP-P) benefits from intermediate supervision through auxiliary node-level labels. Experimental results demonstrate the high accuracy of GEF, with Rou-P achieving 94.56% and ADP-P 94.57 %, respectively. We also conduct ablation studies, which further validate that GEF achieves substantial enhancements through efficient architecture modeling and timingaware analysis. Finally, a case study on routing architecture exploration with the incorporation of GEF is presented, which achieves a$\mathbf{1 5} \boldsymbol{\times}$speedup and enhanced improvements. Our codes are are available from https://github.com/RapidFlex/GEF.

In edge AI inference, FPGAs demonstrate superiority in performance-area balance. FPGA Overlay Accelerators (FOAs) are programmable accelerators implemented on FPGAs, typically highly parameterized to enable flexible hardware realization. These parameters, varying across a wide design space, have a significant impact on performance and require efficient Design Space Exploration (DSE). However, current frameworks struggle to accurately predict performance metrics like maximum frequency and fail to fully explore the design space, limiting DSE's effectiveness. In this paper, we propose a DSE framework for FOA (DEFA) based on Bayesian optimization, providing more effective and comprehensive DSE. To address complex parameter interdependencies in FOA, a dependency-aware design space modeling approach (DAM) is proposed. This approach applies fine-grained pruning to the parameter space while addressing dependency constraints. Based on this pruned parameter space, we develop a custom regression predictor (CREP) for maximum frequency using LightGBM, significantly enhancing performance estimation accuracy. Furthermore, the search efficiency is improved through enhanced Latin hypercube sampling and the Tree-Structured Parzen Estimator. We use the proposed framework to optimize an FOA template, Intel FPGA AI Suite. The Pearson correlation coefficient of CREP's predictions regarding the maximum frequency of accelerator instances achieves 0.87. In the throughput optimization experiment, the proposed DSE framework improves 30.16 % compared to the architecture optimization functionality provided by Intel FPGA AI Suite across the given 10 benchmarks on average. In the areathroughput trade-off optimization experiment, compared with FPGA AI Suite, the proposed DSE framework improves 5.01 % in frequency, 18.48 % in throughput and 21.60 % in area.

High-performance computing (HPC) and hardware acceleration increasingly rely on dataflow architectures to achieve scalable parallelism and efficiency. High-level synthesis (HLS) facilitates accelerator design from high-level programs, but conventional tools often require intrusive source-level modifications and struggle to optimize irregular workloads. Dynamically scheduled HLS frameworks offer a promising direction for addressing control flow divergence and memory irregularity by generating dataflow accelerators. However, they lack compile-time parallelism optimizations such as vectorization and incur significant hardware overhead. Moreover, modern compilers can generate vectorized code using memory access and computational patterns. Nevertheless, in programs with irregular control flow or data-dependent behavior, such patterns are unknown until runtime, limiting the effectiveness of static vectorization strategies.To address these challenges, we propose DynVec, a unified vector-dataflow framework that integrates dynamic scheduling and vectorization to exploit runtime parallelism beyond conventional models. We address the vectorization of irregular kernels through an MLIR-based context-aware vectorizer that effectively identifies vectorizable operations and, through dataflow scheduling, generates a vector-dataflow execution graph that explicitly models control flow constructs, data and control interfaces, and memory operations. DynVec encapsulates high-level elastic units designed with built-in vectorization support, allowing customizable and adaptive execution behavior. Our compiler preserves the structural hierarchy of the kernel by combining vector and scalar operations in a bottom-up, type-safe manner. Experiments show that our approach achieves significant speedup compared to state-of-the-art HLS implementations across various regular and irregular applications. Moreover, compared to hybrid accelerators that separately support dynamic parallelism and vectorization, DynVec delivers superior performance.

Emotion recognition from EEG signals offers significant advantages in affective computing, as EEG more accurately reflects internal emotional states than other modalities, such as facial expressions or peripheral physiological signals. Modeling and capturing subtle affective changes over time is crucial for real-world applications to achieve better human-computer interaction. However, training such models usually requires segment-level emotion labels, which are costly and may not be feasible. Assigning the overall label to all EEG segments within a trial can lead to inaccurate model training and degraded performance, as emotions evolve continuously. This highlights the need for models capable of learning from trial-wise emotion labels while capturing temporal dynamics of emotional responses within each segment because trial-wise post-stimulus labels are more accessible. To this end, we propose EmotionMIL, an end-to-end EEG-based emotion recognition framework that leverages recent advances in deep multiple instance learning (MIL). This framework enables robust emotion recognition from weakly labeled EEG signals and identifies the most prominent emotional responses. EmotionMIL captures the temporal dynamics of emotions using a retentive self-attention mechanism, which adaptively assigns weights to EEG segments based on their relevance in predicting the overall emotion label. A pseudo-bag augmentation strategy is also introduced to enhance the model's generalization ability by generating additional pseudo-bags from the original ones. Evaluated on three benchmark datasets—DEAP, DREAMER, and SEED—EmotionMIL outperforms state-of-the-art non-MIL and MIL models in both subject-dependent and subject-independent tasks, achieving superior accuracy and F1-score. Ablation study further validates the model design, while visualization results demonstrate that EmotionMIL effectively identifies both spatial EEG patterns and temporal emotional dynamics. These findings underscore EmotionMIL's potential for robust, interpretable emotion recognition, paving the way for real-world applications in emotion-aware systems. The code is available athttps://github.com/yuty2009/emotionmil.

Coarse-Grained Reconfigurable Architecture (CGRA) emerges as a competitive accelerator due to its high flexibility and energy efficiency. However, most CGRAs are effective for computation-intensive applications with regular loops but struggle with irregular loops containing control flows. These loops introduce fine-grained logic operations and are costly to execute by coarse-grained arithmetic units in CGRA. Efficiently handling such logic operations necessitates incorporating Boolean algebra optimization, which can improve logic density and reduce logic depth. Unfortunately, no previous research has incorporated it into the compilation flow to support irregular loops efficiently.We proposeCOFFA, an open-source framework for heterogeneous architecture with a RISC-V CPU and a fused-grained reconfigurable accelerator, which integrates coarse-grained arithmetic and fine-grained logic units, along with flexible IO units and distributed interconnects. As a software/hardware co-design framework,COFFAhas a powerful compiler that extracts and optimizes fine-grained logic operations from irregular loops, performs coarse-grained arithmetic and memory optimizations, and offloads the loops to the accelerator.Across various challenging benchmarks with irregular loops,COFFAachieves significant performance and energy efficiency improvements over an in-order, an out-of-order RISC-V CPUs, and a recent FPGA, respectively. Moreover, compared with the state-of-the-art CGRAUE-CGRAandHycube,COFFAcan achieve 2.5× and 3.5× performance gains, respectively.

Coarse-grained reconfigurable architectures (CGRAs) are gaining increasing attention as domain-specific accelerators due to their high flexibility and energy efficiency. These architectures offer a compelling solution for applications that require custom hardware performance while retaining a degree of programmability. However, the design space of CGRAs is inherently vast and complex, presenting significant challenges for architects to explore design choices efficiently and systematically. Existing design space exploration (DSE) methodologies for CGRAs are often time-demanding and struggle to deliver optimal solutions when confronted with high-dimensional and multi-objective design space. Therefore, we consider constructing a CGRA parameter tuning framework called MoDAF. MoDAF initializes the design space using the most representative and diverse samples. It adopts a divide-and-conquer approach, utilizing Monte Carlo Tree Search (MCTS) and space partitioning techniques to dynamically break down the complex design space into more manageable subspaces. A hybrid model handles local fluctuations within each subspace, while a dual sampling algorithm is designed to increase sampling efficiency. MoDAF also incorporates a fast evaluation model to estimate CGRA throughput and area, significantly speeding up the exploration process. Compared with previous approaches, experiments show that our proposed framework reduces the average distance from the reference set by 53.0% and the hypervolume deviation by 64.2%, while also cutting wall time by 57.5%.

As technology scaling exacerbates interconnect resistance in advanced nodes, FPGA architectures demand enhanced programmable logic blocks (PLBs) to minimize global metal routing. However, it is expensive to raise the functionality of LUTs due to exponential area growth with the number of inputs, resulting in poor scalability. Moreover, LUTs are redundant since practical functions in real-world benchmarks only account for an extremely small proportion of all the functions. For example, only 16,424 out of more than 100 trillion NPN classes of 6-input functions are used in the mapped netlists of the VTR8 and KOIOS benchmarks. Therefore, we propose a reduced LUT architecture, named RLUT, to efficiently implement most of the frequent functions. The compact structure of the MUX tree in LUTs is preserved and reduced, while the reduced programmable bits are connected to the MUX tree according to the bit assignment generated automatically by the proposed algorithms. Results of evaluations by a full EDA flow show that, compared with the modified Stratix10 baseline, the proposed 8-input PLB with 75 SRAM bits, named Dual-RLUT6, reduces the maximum logic levels significantly by 20.85%, while the critical path delay is improved by 10.11% at the cost of 4.65% area overhead.

In this paper, we propose a domain-specific frame-work that integrates Chisel-based Coarse-grained reconfigurable architecture (CGRA) Modeling, RTL generation, Architecture Graph Intermediate Representation (IR), dataflow graph (DFG) Mapping, interconnect exploration, and physical implementation. Within this framework, we propose an interconnect exploration flow based on a novel interconnect architecture called Matrix, which realizes a heterogeneous interconnect architecture for a set of specific applications by application mapping, design space exploration (DSE) and pruning. We design an agile mapper built on a graph-based two-level architectural IR, which better adapts to the flexible interconnect model and enables greater interconnect exploration to improve the mapping success rate. Experiments show a significant reduction in architecture area, improved energy efficiency, and high PE utilization compared to the state-of-the-art tool, with high-quality mapping results due to architecture tuning. Additionally, our pruning strategies reduce interconnect paths in the Matrix, ensuring interconnect efficiency and further improving PE utilization.

Coarse-grained reconfigurable architecture (CGRA) is a type of reconfigurable computing architecture suitable for emerging applications that require dynamic compilation hardware. However, the resource utilization of existing CGRA is low due to the lack of flexibility across varied application granularity. In this paper, we propose a CGRA framework for multiple dataflow lanes (MDCRA). It supports post-silicon computational granularity adjustments. Evaluated with Polybench, Machsuite and Express, the speedup of MDCRA is$24.83\times$higher than CPU CVA6, and$2.08\times$higher than vector processor Ara. Compared with TRAM and DSAGEN, MDCRA achieves an area reduction of 27% and 47% respectively with the same speedup. Besides, compared with OpenCGRA, the average utilization of function units is improved by 20.05%.

Coarse-grained reconfigurable architecture (CGRA) gradually becomes an extraordinarily promising accelerator due to its flexibility and power efficiency. However, most CGRA front-end compilers focus on the innermost body of regular loops with a pure data flow. Therefore, we propose CO-Compiler, an LLVM-based CGRA front-end compiler to generate an optimized control-data flow graph (CDFG), which can handle versatile loops in C/C++, including general control flow, arbitrary nested levels, and imperfect statements. Then we extract multi-dimension memory access patterns and various dedicated operators adapting to concrete hardware functions. In addition, we analyze variable loop bounds which are settled at runtime, and realize the SoC runtime configuration of CGRA. The feasibility of our methodology is verified by a RISC-V based SoC simulation. The experimental results demonstrate that our dedicated operator extraction can reduce 43% PE resources and decrease 84% initiation interval (II) on a TRAM architecture. Furthermore, compared with state-of-the-art (SOTA) CGRA front-end compilers, CO-Compiler has the highest 88.1% success rate in CDFG generation for a wide range of benchmarks. Moreover, by using the same back-end mappers, our work can reach 78% reduction for II and $2.06\times$ PE spatio-temporal utilization in contrast with their own front-end compilers.

Adopting specialized accelerators such as Coarse-Grained Reconfigurable Architectures (CGRAs) alongside CPUs to enhance performance within specific domains is an astute choice. However, the integration of heterogeneous architectures introduces complex challenges for compiler design. Simultaneously, the ever-expanding scale of workloads imposes substantial burdens on deployment. To address above challenges, this paper introduces CGRV-OPT, a user-friendly multi-level compiler designed to deploy large-scale workloads to CGRA and RISC-V CPU architecture. Built upon the MLIR framework, CGRV-OPT serves as a pivotal bridge, facilitating the seamless conversion of high-level workload descriptions into low-level intermediate representations (IRs) for different architectures. A salient feature of our approach is the automation of a comprehensive suite of optimizations and transformations, which speed up each kernel computing within the intricate SoC. Additionally, we have seamlessly integrated an automated software-hardware partitioning mechanism, guided by our multi-level optimizations, resulting in a remarkable 2.14 × speed up over large-scale workloads. The CGRV-OPT framework significantly alleviates the challenges faced by software developers, including those with limited expertise in hardware architectures.

Convolutional neural networks (CNNs) and transformer neural networks have been adopted in a wide range of applications such as natural language processing and computer vision. Coarse-grained reconfigurable architectures (CGRAs) are highly suitable for CNN and transformer applications due to their high flexibility and energy efficiency. However, current implementations of CGRA for CNNs and transformers have several limitations including the lack of System-on-Chip (SoC), insufficient support for nonlinear functions and the absence of a software toolchain. To address these challenges, we present CFEACT, a CGRA-based framework that enables agile development of CNN and transformer accelerators. CFEACT offers a broad design space of efficient CGRA accelerators through a highly flexible architecture template. The well-designed SoC, innovative mapping schemes, and comprehensive software toolchain offer a complete solution for implementing various CNN and transformer models on the generated CGRAs. Compared with the state-of-the-art works, accelerators generated by CFEACT can achieve more than $2 \times$ improvement in area-delay product for CNNs and an average of $2 \times$ higher performance for transformers.

Silicon interposer re-usage is drawing attention for cost-effective multi-chiplet integrated systems. To address the communication awareness of inter/off-chiplet interconnect, the paper proposes a field-programmable interconnect fabric and develops its corresponding automatic physical integration tool. The tile-based fabric consists of turnout, cross-over boxes and parallel tracks. It features micro-bump-wise connecting flexibility and hardware efficiency. The automation flow performs chiplet location optimization and efficient bump-to-bump routing, supporting multi-lane bus interconnect and miscellaneous external ports. The methodology is validated by 9 different integration scenarios, where the routability is guaranteed when the local resource utilization ratio approaches 94.5%. The data’s maximum interconnect latency is 2.2 ns and the energy consumption is 1.18 pJ/bit at a bitrate of 1 Gbps. The latency consumes$16.5\times \sim ~53.4\times $fewer clock cycles than the state-of-the-art network-on-package-based reusable interposer architectures.

Logic synthesis is a crucial step in electronic design automation tools. The rapid developments of reinforcement learning (RL) have enabled the automated exploration of logic synthesis. Existing RL based methods may lead to data inefficiency, and the exploration approaches for FPGA and ASIC technology mapping in recent works lack the flexibility of the learning process. This work proposes ESE, a reinforcement learning based framework to efficiently learn the logic synthesis process. The framework supports the modeling of logic optimization and technology mapping for FPGA and ASIC. The optimization for the execution time of the synthesis script is also considered. For the modeling of FPGA mapping, the logic optimization and technology mapping are combined to be learned in a flexible way. For the modeling of ASIC mapping, the standard cell based optimization and LUT optimization operations are incorporated into the ASIC synthesis flow. To improve the utilization of samples, the Proximal Policy Optimization model is adopted. Furthermore, the framework is enhanced by supporting MIG based synthesis exploration. Experiments show that for FPGA technology mapping on the VTR benchmark, the average LUT-Level-Product and script runtime are improved by more than 18.3% and 12.4% respectively than previous works. For ASIC mapping on the EPFL benchmark, the average Area-Delay-Product is improved by 14.5%.

Coarse-grained reconfigurable arrays (CGRAs) are promising design choices in computation-intensive domains, since they can strike a balance between energy efficiency and flexibility. A typical CGRA comprises processing elements (PEs) that can execute operations in applications and interconnections between them. Nevertheless, most CGRAs suffer from the ineffectiveness of supporting flexible architecture design and solving large-scale mapping problems. To address these challenges, we introduce HierCGRA, a novel framework that integrates hierarchical CGRA modeling, Chisel-based Verilog generation, LLVM-based data flow graph (DFG) generation, DFG mapping, and design space exploration (DSE). With the graph homomorphism (GH) mapping algorithm, HierCGRA achieves a faster mapping speed and higher PE utilization rate compared with the existing state-of-the-art CGRA frameworks. The proposed hierarchical mapping strategy achieves 41× speedup on average compared with the ILP mapping algorithm in CGRA-ME. Furthermore, the automated DSE based on Bayesian optimization achieves a significant performance improvement by the heterogeneity of PEs and interconnections. With these features, HierCGRA enables the agile development for large-scale CGRA and accelerates the process of finding a better CGRA architecture.

Coarse-grained reconfigurable architectures (CGRAs) have emerged as promising accelerators due to their high flexibility and energy efficiency. However, existing open source works often lack integration of CGRAs with CPU systems and corresponding toolchains. Moreover, there is rare support for the accelerator instruction pipelining to overlap data communication, computation, and configuration across multiple tasks. In this article, we propose FDRA, an open source exploration framework for a heterogeneous system-on-chip (SoC) with a RISC-V processor and a dynamically reconfigurable accelerator (DRA) supporting loop, instruction, and task levels of parallelism. FDRA encompasses parameterized SoC modeling, Verilog generation, source-to-source application code transformation using frontend and DRA compilers, SoC simulation, and FPGA prototyping. FDRA incorporates the extraction of periodic accumulative operators and multi-dimensional linear load/store operators from nested loops. The DRA enables accessing the shared L2 cache with virtual addresses and supports direct memory access with arbitrary start addresses and data lengths. Integrated into the RISC-V Rocket SoC, our DRA achieves a remarkable 55× acceleration for loop kernels and improves energy efficiency by 29×. Compared to state-of-the-art RISC-V vector units, our DRA demonstrates a 2.9× speed improvement and 3.5× greater energy efficiency. In contrast to previous CGRA+RISC-V SoCs, our SoC achieves a minimum speedup of 5.2×.

Due to its high energy efficiency and flexibility, coarse-grained reconfigurable architecture (CGRA) has gained increasing attention. Temporal CGRA is a typical category of CGRA that supports single-cycle context switching and time-multiplexing hardware resources to perform spatial and temporal computations. Although multiple temporal CGRAs have been proposed, an architecture with rich design parameters and heterogeneous modeling is still lacking. To this end, we propose a highly parameterized heterogeneous temporal CGRA, called HETA. However, the highly parameterized and heterogeneous design introduces a challenging design space for manual exploration. To address this challenge, we introduce a Bayesian-optimization (BO)-based design space exploration (DSE) of homogeneous and heterogeneous architectures. Different from other DSE processes that require defining the heterogeneous exploration strategy, our approach adopts a searching-pruning-based method without manual intervention. To improve the efficiency of DSE, we develop a fast statistic model for area evaluation, whose error is below 1%. In addition, a pipeline mapping (PiPMap) algorithm is developed to alleviate the restrictions caused by data synchronization and unleash the potential of the proposed architecture. Experimental results show that HETA can achieve 89%, 52%, and 47% improvement in throughput, area efficiency, and energy efficiency over the neighbor-to-neighbor (N2N)-based interconnect CGRA, respectively. Compared with the Switch-based interconnect CGRA, HETA’s area efficiency is increased by 61%. Furthermore, compared with the homogeneous architecture of HETA, the optimized heterogeneous architecture improves area efficiency and energy efficiency by 14.7% and 4.8%, respectively.

We present a efficient multi-view inverse rendering method for large-scale real-world indoor scenes that reconstructs global illumination and physically-reasonable SVBRDFs. Unlike previous representations, where the global illumination of large scenes is simplified as multiple environment maps, we propose a compact representation called Texture-based Lighting (TBL). It consists of 3D mesh and HDR textures, and efficiently models direct and infinite-bounce indirect lighting of the entire large scene. Based on TBL, we further propose a hybrid lighting representation with precomputed irradiance, which significantly improves the efficiency and alleviates the rendering noise in the material optimization. To physically disentangle the ambiguity between materials, we propose a three-stage material optimization strategy based on the priors of semantic segmentation and room segmentation. Extensive experiments show that the proposed method outperforms the state-of-the-art quantitatively and qualitatively, and enables physically-reasonable mixed-reality applications such as material editing, editable novel view synthesis and relighting. The project page is at https://lzleejean.github.io/TexIR.

Temporal Coarse-Grained Reconfigurable Architecture (CGRA) is a typical category of CGRA that supports single-cycle context switching and time-multiplexing hardware resources to perform both spatial and temporal computations. Compared with the spatial CGRA, it can be used in area and power budget-constrained scenarios, with the sacrifice of the throughput. Therefore, achieving minimum Initialization Interval (II) for higher throughput is the main objective in many works for temporal CGRA mapping.

Coarse-Grained Reconfigurable Architecture (CGRA) is a domain-specific reconfigurable architecture. Generally, the CGRA architecture consists of IO, memory, coarse-grained processing element (PE), and interconnect. Usually, ALU in PE contains a relatively complete set of operations and most of the interconnects adopt neighbor-to-neighbor (N2N) [1], switch-based [2], and combination of the connection box and switch box (CB-SB) patterns [3]. However, the complex operation sets and switch-based/CB-SB fully-connected interconnects provide sufficient reconfigurability at the cost of resource overhead. Thus, it is important to build a parameterized architecture of CGRA to achieve a balance among hardware overhead, flexibility and performance through automatic design space exploration (DSE).

Coarse-grained reconfigurable architecture (CGRA), composed of word-level processing elements (PEs) and interconnects, has emerged as a promising architecture due to its high performance, energy efficiency, and flexibility. Although multiple CGRA frameworks have been proposed, a complete heterogeneous CGRA exploration framework with tunable interconnect flexibility and fast design space exploration (DSE) is still lacking. In this paper, we propose an open-source template-based CGRA exploration framework that integrates the modeling of heterogeneous PEs and interconnects, RTL generation, DFG mapping, automatic simulation and verification, and fast DSE based on a CGRA framework TRAM. Moreover, we present a novel resource-efficient shared reconfigurable delay unit (RDU) for data synchronization, which can save the CGRA area by 7%, compared with the separated RDU. Further, the explored optimal heterogeneous architecture can reduce the area and power by 44.7% and 42.9% respectively, and improve the PE utilization by 20.4%, compared with the 8 × 8 baseline architecture in TRAM.

Research on recommender systems has noted that the ranking of recommended items may play an important role in the performance of recommendation algorithms. To advance recommender systems research beyond the traditional approach that ranks recommended products in descending, it is crucial to understand the cognitive processes that online consumers experience when they evaluate products in a sequence. Drawing on evaluability theory and the order effects perspective, we formulate a scenario in which two products are presented sequentially and each product has two attributes, one of which can be evaluated independently while the other is difficult to evaluate without comparison. Analyses show that in two out of the three cases examined, presenting the most recommended product in the second place will result in stronger consumer purchase intentions and willingness to pay. Research hypotheses are proposed based on the results of the scenario analyses and are empirically tested through three laboratory experiments. In Study 1, evidence for the hypothesized order effects is found for the settings with randomly assigned product recommendations. In Study 2, the same effects are observed for the settings with personalized recommendations generated by a collaborative filtering algorithm. In Study 3, it is shown that such order effects also exist in terms of the recommendation strength of recommender systems. These findings provide novel insights into the behavioral implications of using recommender systems in e-commerce, shedding light on additional means of improving the design of such systems.

Field-programmable gate arrays (FGPAs) are widely used because of the superiority in flexibility and lower non-recurring engineering cost. How to optimize the routing architecture is a key problem for FPGA architects because it has a large impact on FPGA area, delay, and routability. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs), whereas most research has focused on SB architectures, such as Wilton, Universal, and Disjoint SB patterns. In this article, we propose a novel unidirectional routing architecture—general interconnection block (GIB)—to improve FPGA performance. With the GIB architecture, logic block (LB) pins can directly connect with the adjacent GIBs without programmable switches. Inside a GIB, LB pins can connect to the routing channel tracks on the four sides of a GIB. In particular, the logic pins from different neighboring LBs that connect to the same GIB can connect with each other with only one programmable switch. In addition, we enhance VTR to support the GIB with bent wires and develop a searching framework based on the simulated annealing algorithm to search for a near-optimal distribution of wire types. We evaluate the GIB architecture on VTR 8 with the provided benchmark circuits. The experimental results show that the GIB architecture with length-4 wires can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product compared to the VTR CB-SB architecture with length-4 wires. After exploring mixed wire types, the optimized GIB architecture can further improve the delay by 16.4% and area-delay product by 17.1% compared to the CB-SB architecture with length-4 wires.

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs.

Inverse rendering of complex material such as glossy, metal and mirror material is a long-standing ill-posed problem in this area, which has not been well solved. Previous approaches cannot tackle them well due to simplified BRDF and unsuitable illumination representations. In this paper, we present PhyIR, a neural inverse rendering method with a more completed SVBRDF representation and a physics-based in-network rendering layer, which can handle complex material and incorporate physical constraints by re-rendering realistic and detailed specular reflectance. Our framework estimates geometry, material and Spatially-Coherent (SC) illumination from a single indoor panorama. Due to the lack of panoramic datasets with completed SVBRDF and full-spherical light probes, we introduce an artist-designed dataset named FutureHouse with high-quality geometry, SVBRDF and per-pixel Spatially-Varying (SV) lighting. To ensure the coherence of SV lighting, a novel SC loss is proposed. Extensive experiments on both synthetic and real-world data show that the proposed method outperforms the state-of-the-arts quantitatively and qualitatively, and is able to produce photorealistic results for a number of applications such as dynamic virtual object insertion.

Coarse-grained reconfigurable architecture (CGRA) is a promising accelerator design choice due to its high performance and power efficiency in the computation or data-intensive application domains, such as security, multimedia, digital signal processing, machine learning, and high-performance computing. CGRA consists of coarse-grained processing elements (PEs) and interconnects that determine the architecture flexibility to support different applications and also affect the performance and power efficiency significantly. Although multiple types of interconnects have been proposed, a parameterized unified model is still lacking. In this paper, we propose a flexible and scalable CGRA template with a novel interconnect model that can unify the typical neighbor-to-neighbor, switch-based, and FPGA-like interconnects. Furthermore, we present TRAM, an open-source template-based reconfigurable architecture modeling framework that integrates the Chisel-based CGRA modeling, architecture intermediate representation (IR) and Verilog generation, dataflow graph (DFG) mapping, simulation, and evaluation. The mapping flow contains graph-based placement and routing, critical-path-driven data synchronization, and simulated-annealing-based optimization. We evaluate the impacts of the rich design parameters, which demonstrate the significance of such a flexible template to facilitate architecture optimization. Compared with the related work, TRAM can achieve a 4.1× smaller DFG latency and a faster mapping speed for both the 8×8 and 16×16 CGRAs. Moreover, TRAM is able to attain an extremely high PE utilization of 94.4 % on average by architecture tuning.

Modern FPGAs utilize complex routing architectures to optimize the area, critical path delay, and power consumption. General Routing Block (GRB) models the routing resources of modern FPGAs, enabling the design of better routing architectures than previous academic FPGAs based on the CB-SB model. However, the design space of the GRB model is too large to be explored manually. In this paper, we propose GRAEBO, a design space exploration (DSE) algorithm for FPGA routing architectures based on Bayesian optimization, which can optimize and accelerate the DSE by balancing exploration and exploitation. Moreover, we design pruning rules to further improve the DSE efficiency, which can serve as a multi-fidelity acceleration method. GRAEBO obtains better area, delay, and area-delay product than a 142-channel baseline CB-SB architecture, with improvements of 8%, 19%, and 26%, respectively. Compared to the GRB architecture found by the simulated annealing algorithm, GRAEBO achieves 9% smaller area, 5% shorter delay, and 13% better area-delay product on the VTR benchmarks.

Logic synthesis is a crucial step in electronic design automation tools for integrated circuit design. In recent years, the development of reinforcement learning (RL) has enabled the designers to automatically explore the logic synthesis process. Existing RL based methods typically use conventional on-policy models, which leads to data inefficiency. Moreover, the exploration approach for FPGA technology mapping in recent works lacks the flexibility of the learning process. In this work, we propose ESE, a reinforcement learning based framework to efficiently learn the logic synthesis process. The framework supports the modeling for both the logic optimization and the FPGA technology mapping. The reward functions and terminal conditions in the RL environment are designed to efficiently guide the optimization of the metrics and execution time. For the modeling of FPGA mapping, the logic optimization and technology mapping are combined to be learned in a flexible way. Moreover, the Proximal Policy Optimization model is adopted to improve the utilization of samples. The proposed framework is evaluated on several common benchmarks. For the logic optimization on the EPFL benchmark, compared with previous works, the proposed method obtains an 11.3% improvement in the average quality (node-level-product) and reduces the execution time by 13.7%. For the FPGA technology mapping on the VTR benchmark, our method improves the average quality (LUT-level-product) by 14.8%, and reduces the execution time by 14.4% compared with the recent work.

In this paper, two approximate 3 × 3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31.38% and 36.17%, and the power consumption by 36.73% and 35.66% compared with the exact multiplier, respectively. They can be aggregated with a 2 × 2 multiplier to produce an 8 × 8 multiplier with low error-rate based on the distribution of DNN weights. We propose a hardware-driven software co-optimization method to improve the DNN accuracy by retraining. Based on the proposed two approximate 3-bit multipliers, three approximate 8-bit multipliers with low error-rate are designed for DNNs. Compared with the exact 8-bit unsigned multiplier, our design can achieve a significant advantage over other approximate multipliers on the public dataset.

We propose an optimization method for the automatic design of approximate multipliers, which minimizes the average error according to the operand distributions. Our multiplier achieves up to 50.24% higher accuracy than the best reproduced approximate multiplier in DNNs, with 15.76% smaller area, 25.05% less power consumption, and 3.50% shorter delay. Compared with an exact multiplier, our multiplier reduces the area, power consumption, and delay by 44.94%, 47.63%, and 16.78%, respectively, with negligible accuracy losses. The tested DNN accelerator modules with our multiplier obtain up to 18.70% smaller area and 9.99% less power consumption than the original modules.

Nonvolatile memory express (NVMe) is a high-performance and scalable PCI express (PCIe)-based interface for the host software communicating with NVMs, including NAND Flash and the storage class memories (SCMs). NVMe solid-state drives (SSDs) have been deployed in cloud platforms and data-centers for a variety of I/O intensive applications due to their performance benefits compared to SATA/SAS SSDs. Considering the design flexibility, firmware-based NVMe controllers are typically used in Flash-based NVMe SSDs but may occupy a significant portion of processor resources and power consumption to achieve high performance. Moreover, the firmware component can be a critical performance bottleneck for SCMs that are an order-of-magnitude faster than Flash. To address these challenges, hardware-accelerated NVMe controllers have emerged in both industry and academia. The commercial hardware controllers are confidential, whereas current academic studies still spare much room for architecture innovations. In this article, we propose an opensource ultralow-latency and high-throughput NVMe controller with a highly parallel, pipelined, and scalable architecture that accommodates one admin controller and multiple fully hardware-automated I/O controllers. We perform extensive empirical performance evaluations concerning the NVMe I/O size, queue depth, queue number, read-to-write ratio, and access pattern. The maximum read/write bandwidth can achieve 7.0 GB/s, accounting for 89% of the PCIe bandwidth. The 4-KB-sized read/write throughput can attain 1.7 million I/O operations per second (MIOPS), whereas the average latency is merely 2.4$\mu \text{s}$/3.2$\mu \text{s}$. Compared to state-of-the-art NVMe controllers in academia, the 4-KB-sized read/write bandwidth of our controller reaches$2.2 \times /2.3\times $as high and the latency is$5.1 \times /4.9\times $lower.

Approximate computing is an efficient approach to reduce the design complexity for error-resilient applications. Multipliers are key arithmetic units in many applications, such as deep neural networks (DNNs) and digital signal processing (DSP) systems. In this article, an open-source adaptable approximate multiplier design driven by input distribution and polarity is proposed to generate optimized approximate multipliers to trade off between the application-level performance and the hardware cost. The proposed method minimizes the average square of the absolute error of an approximate multiplier according to the probability distributions of operands extracted from the target application with consideration of input polarity, achieving low hardware cost and negligible application-level performance loss. The proposed method can generate unsigned multipliers (or signed multipliers) based on the Braun multiplier (or Baugh–Wooley multiplier). To demonstrate the effectiveness of the method, three different-scale quantized DNNs, including LeNet, AlexNet, and VGG16 with 8$\times $8 unsigned multiplication and an adaptive least mean square (LMS)-based finite impulse response (FIR) filter with 16$\times $16 fixed-point signed multiplication, are evaluated. In the DNN training process, a noise training technique is adopted to reduce the accuracy loss due to the approximation. When compared to the state-of-the-art approximate multipliers, the generated multipliers can achieve up to 26.4% and 27.1% product of power, delay, and area gains with negligible application-level performance loss in VGG16 and FIR applications, respectively.

NAND-Flash-based SSDs have been widely employed in diverse computing domains and storage systems due to their higher performance and lower power consumption than HDDs. There have been various studies to explore the internal parallelism inside SSDs, including the channel-way-plane levels of interleaving and the cache mode pipelining. However, most current studies are based on simulators or focus on part of the parallelism. In this paper, we present an open-source high-performance open-channel open-way NAND Flash controller supporting all the parallelism. Several architecture innovations are proposed to improve performance and resource efficiency. Firstly, the controller exposes the multi-channel, multi-way topology with a queue-based asynchronous interface for each way. Secondly, a dual-level command scheduler is integrated to enable the fine-grained way-level interleaving, plane-level interleaving, and cache mode pipelining. Finally, four finite state machines are designed for the classified Flash command groups. Evaluated on an FPGA platform, the maximum bandwidth can reach 1.2GB/s, accounting for 93% of the theoretical bandwidth, 13% higher than the bandwidth utilization of other Flash controllers. The minimum latencies for the page reading and programming are 119ps and 2ms respectively, which can be further speeded up by 1.9x and 3.1x on average with the multi-level parallelism.

In FPGAs, the programmable interconnect is implemented by multiplexers (MUXes), which have a large impact on the area and delay. In academia, large MUXes are extensively used in intra and inter clusters, resulting in significant FPGA area overhead and load for routing wires. In this paper, we model the interconnect from routing wires and CLB feedbacks to LUT inputs as an input block (IB), and implement the IB and the switch block (SB) with the 2-level MUX topology. Applying the 2-level MUX topology in FPGA routing architecture enables us to explore a larger design space for the area and delay, because the 2-level MUX topology can tradeoff between MUX sizes, connectivity degree, and the input bandwidth. We carefully design a baseline 2-level MUX routing architecture and evaluate it by running place and route experiments with VTR benchmarks. To optimize the baseline 2-level MUX routing architecture, we explore one design parameter at a time by keeping others fixed and perform subsequent explorations based on previous optimal design parameters. The results show that the optimized 2-level MUX routing architecture can achieve 1% shorter critical path delay (CPD) at the cost of 3% area overhead compared to the CB-SB FPGA architecture with 1-level MUX topology.

In error-tolerant applications such as low-precision DNNs and digital filters, approximate arithmetic circuits can significantly reduce hardware resource utilization. In this work we propose an embedded block for field-programmable gate arrays, called APIR-DSP, which incorporates an approximate 9×9 hard multiplier based on the PIR-DSP architecture to improve speed and reduce area. In addition, a DSP unit evaluation platform based on Yosys and VPR which packs multiply accumulate operations into DSP blocks is developed. Using this tool we synthesis designs from Verilog implementations of matrix multiplication in DeepBench and the DoReFaNet low-precision neural network and show that APIR-DSP significantly reduces DSP resources and improves hardware utilization and performance compared with the Xilinx DSP48E2 embedded block. Compared with exact multiplication, it is shown that accuracy loss is optimized with the SNR of an FIR filter being reduced by 1.03 dB. For DNNs, accuracy loss for AlexNet is 0.31% on CIFAR10 dataset and no accuracy loss for LeNet on MNIST dataset is observed. Synthesis results show that the APIR-DSP enjoys an area reduction of 21.60%, critical path reduction of 4.85% and power consumption is reduced by 2.80%, compared with PIR-DSP.

Nonlinear activation functions (NAFs) play an essential role in deep neural networks (DNNs). Since versatile DNN accelerators need to support various DNNs which contain different NAFs, the flexible hardware design supporting those NAFs has become crucial. However, there are few high-precision flexible hardware architectures, and the symmetries of different NAFs have not been fully studied. This paper proposes a high-precision symmetry-aware architecture based on piecewise linear approximation. Through the reconfigurable data path, the architecture can support various typical NAFs. The efficient non-uniform segmentation scheme is proposed to achieve high precision for each NAF. Besides, the utilization of unified symmetry for NAFs can save half the memory. To reduce the computational cost, a 25×18 DSP is shared by two INT 7×9 multipliers with two independent inputs. The architecture is implemented on Xilinx ZC706 at a frequency of 410MHz. Compared with the state-of-the-art flexible nonlinear core, our flexible architecture costs fewer hardware resources with higher precision. Applying the design to BERT-BASE, MobileNetV3, and EfficientNet-B3 on the PyTorch platform, experimental results show that the accuracy loss is either 0 for BERT-BASE, or 0.002% for EfficientNet-B3. For MobileNetV3, the accuracy is even improved by 0.01%.

Lightweight convolutional neural networks (CNNs) have become increasingly popular due to their lower computational complexity and fewer memory accesses with equivalent accuracy compared to previous CNN models. However, the newly proposed networks bring new challenges to efficient hardware design, such as, in EfficientNet, depthwise convolution, squeeze-and-excitation (SE) module, and swish/sigmoid functions. Although individual engine architecture could achieve a high computing efficiency for the standard convolution or the depth-wise convolution, it is still not efficient for EfficientNet because the workload imbalance between two types of convolutional engines causes inevitable idling. To overcome this problem, we present a lightweight reconfigurable computational kernel based on FPGA with an exchangeable-track datapath scheme. In addition, a low-accuracy-loss function replacement strategy is proposed for swish/sigmoid functions. Furthermore, the low-cost hardware architecture to implement the replaced functions is designed. The proposed accelerator (LETA) can implement EfficientNet on Xilinx XCVU37P with a 300 MHz system clock and a 600 MHz kernel clock. The linear growth of resource usage in the 4-kernel implementation in 1 super logic region (SLR) with the same clock frequencies justifies the scalability of LETA. The experimental results show that LETA can achieve 2× throughput/DSP compared to the latest FPGA-based accelerator with 1.6% (0.7%) top-1 (top-5) accuracy loss on EfficientNet-B3.

Routing architecture has a significant impact on the area, critical path delay and power consumption of modern FPGAs. The most common routing architecture of island-style FPGAs in academia is the CB-SB model, which is not effective to model complex routing architectures in modern FPGAs. To improve the routability and performance of the existing routing model, we propose a new routing model called General Routing Block (GRB) to model complex commercial FPGAs. In the proposed model, all routing resources can be divided into three modules: general switch block (GSB), input connection block (ICB) and output connection block (OCB). The GSB and ICB are extended from the SB and CB with more flexible and richer connections. The OCB is a new module that provides novel connections for the LB output pins. We support bent wire architecture to reduce the delay, and two-level MUXes with output sharing to achieve a better trade-off between the area and flexibility. Moreover, to explore the trade-offs of different design spaces and find better architectures, an architecture exploration platform based on the simulated annealing algorithm is proposed to efficiently explore the enormous design space specified by a set of parameters. The results of global design space exploration show that the architecture with the proposed GRB model reduces the critical path delay by 15.5% and area-delay product by 14.8% compared to the length-4 CB-SB architecture based on the VTR benchmarks. After further local subspace explorations, the best architecture can achieve an 18.7% improvement on the critical path delay and a 23.8% improvement on the area-delay product, which represents a significant improvement over other routing architectures.

Field Programmable Gate Arrays (FPGAs) are widely used for their flexibility and short time to market. FPGA routing architecture design is the key problem due to the fact that it plays a dominant role in the area, delay and power. Most of modern FPGAs are island-style which provide abundant vertical and horizontal tracks to guarantee the circuit designs can be routed successfully. Most connections in placed netlists are diagonal which may lead to passing through extra turning switches, resulting in increased delay cost and high routing density. In this paper, we propose a hexagon-based honeycomb FPGA routing architecture to improve the routability and performance. In honeycomb architecture, there are three kinds of routing channels which can provide more freedom to decrease the turning switches on the routing paths. In addition, the router lookahead algorithm is enhanced to support the honeycomb architecture which is then evaluated by the enhanced VTR with provided benchmarks. The experimental results show that the honeycomb architecture can improve the minimum routing channel width by 7.7% compared with traditional rectangular architecture with length-1 wires. In addition, the honeycomb architecture can achieve 9.9% improvement on the routed wirelength, 11.5% on the critical path delay and 12.4% on the area-delay product.

Technology mapping from logic netlists to programmable logic blocks (PLB) plays an important role in FPGA EDA flow, especially for architecture exploration of PLBs. However, technology mapping becomes time-consuming due to the booming scale and complexity of IC designs as well as the growing complexity of PLB architectures. To speed up this process, a parallelized technology mapping approach based on adaptive circuit partitioning is proposed in this paper to perform fast multi-thread technology mapping. First, We choose the best of the three candidate partitioning strategies for the given netlist by circuit analysis to partition the original netlist into several independent sub-netlists. Secondly, these sub-netlists are mapped to the given PLB architecture simultaneously in their corresponding mapping threads. Finally, the complete mapped netlist is generated by merging the mapped sub-netlists. The proposed approach is implemented in ABC, independent of the detailed mapping algorithm. 13 large circuits from the Titan23 benchmark set are used as benchmarks to evaluate the proposed approach. Experimental results show that the proposed approach leads to an average of 5.76 × speedup over the single-thread version (up to 8.21 × individually) with no delay loss and less than 0.57% average area penalty.

Coarse-Grained Reconfigurable Arrays (CGRAs) provide sufficient flexibility in domain-specific applications with high hardware efficiency, which make CGRAs suitable for fast-evolving fields such as neural network acceleration and edge computing. To meet the requirement of the fast evolution, we propose FastCGRA, the modeling, mapping, and exploration platform for large-scale CGRAs. FastCGRA supports hierarchical architecture description and automatic switch module generation. Connectivity-aware packing and graph partition algorithms are designed to reduce the complexity of placement and routing. The graph homomorphism placement algorithm in FastCGRA enables efficient placement on large-scale CGRAs. The packing and placement algorithms cooperate with a negotiation-based routing algorithm to form an integral mapping procedure. FastCGRA can support the modeling and mapping of large-scale CGRAs with significantly higher placement and routing efficiency than existing platforms. The automatic switch module generation method can reduce the complexity of CGRA interconnection design. With these features, FastCGRA can boost the exploration of large-scale CGRAs.

Despite the powerful expressivity of neural networks with nonlinear activation functions, the underlying mechanism for deep neural networks still remains unclear. However, it can be proved that ultra-wide neural networks are equivalent to Gaussian processes, thus connecting the analysis on neural networks with Bayesian statistics and kernel methods. Moreover, recent studies on infinitely wide neural networks extend this correspondence to a specific kernel, named Neural Tangent Kernel (NTK), which governs the learning dynamics of related neural networks. Without weights and biases, the NTK recursively encodes the architecture information about the corresponding neural networks, including the activation function at each hidden layer. Inspired by this close relationship of Gaussian processes and neural networks, we propose a heuristic search method for activation functions of sufficiently wide neural networks in the NTK regime. To obtain an elegant and closed-form computation, activation functions are decomposed in the basis of Hermite polynomials, which converts the kernels in Gaussian processes into power series. Experiments show the outperformance of the obtained nonlinearities compared with other common activation functions. This work also reveals the potential utility of NTKs for guidance on neural network structure search in the future.

BACKGROUND: Brain tumor segmentation is a challenging problem in medical image processing and analysis. It is a very time-consuming and error-prone task. In order to reduce the burden on physicians and improve the segmentation accuracy, the computer-aided detection (CAD) systems need to be developed. Due to the powerful feature learning ability of the deep learning technology, many deep learning-based methods have been applied to the brain tumor segmentation CAD systems and achieved satisfactory accuracy. However, deep learning neural networks have high computational complexity, and the brain tumor segmentation process consumes significant time. Therefore, in order to achieve the high segmentation accuracy of brain tumors and obtain the segmentation results efficiently, it is very demanding to speed up the segmentation process of brain tumors. RESULTS: Compared with traditional computing platforms, the proposed FPGA accelerator has greatly improved the speed and the power consumption. Based on the BraTS19 and BraTS20 dataset, our FPGA-based brain tumor segmentation accelerator is 5.21 and 44.47 times faster than the TITAN V GPU and the Xeon CPU. In addition, by comparing energy efficiency, our design can achieve 11.22 and 82.33 times energy efficiency than GPU and CPU, respectively. CONCLUSION: We quantize and retrain the neural network for brain tumor segmentation and merge batch normalization layers to reduce the parameter size and computational complexity. The FPGA-based brain tumor segmentation accelerator is designed to map the quantized neural network model. The accelerator can increase the segmentation speed and reduce the power consumption on the basis of ensuring high accuracy which provides a new direction for the automatic segmentation and remote diagnosis of brain tumors.

Many convolutional neural network (CNN) accelerators are proposed to exploit the sparsity of the networks recently to enjoy the benefits of both computation and memory reduction. However, most accelerators cannot exploit the sparsity of both activations and weights. For those works that exploit both sparsity opportunities, they cannot achieve the stable load balance through a static scheduling (SS) strategy, which is vulnerable to the sparsity distribution. In this work, a balanced compressed sparse row format and a dynamic scheduling strategy are proposed to improve the load balance. A set-associate structure is also presented to tradeoff the load balance and hardware resource overhead. We propose SWM to accelerate the CNN inference, which supports both sparse convolution and sparse fully connected (FC) layers. SWM provides Winograd adaptability for large convolution kernels and supports both 16-bit and 8-bit quantized CNNs. Due to the activation sharing, 8-bit processing can achieve theoretically twice the performance of the 16-bit processing with the same sparsity. The architecture is evaluated with VGG16 and ResNet50, which achieves: at most 7.6 TOP/s for sparse-Winograd convolution and three TOP/s for sparse matrix multiplication with 16-bit quantization on Xilinx VCU1525 platform. SWM can process 310/725 images per second for VGG16/ResNet50 with 16-bit quantization. Compared with the state-of-the-art works, our design can achieve at least 1.53 × speedup and 1.8 × energy efficiency improvement.

We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the first tier, we augment existing commercial logic cell datapaths with a 6-input XOR gate in order to improve the expressiveness of each element, while maintaining backward compatibility. This new architecture is vendor-agnostic, and we refer to it as LUXOR. We also consider a secondary tier of vendor-specific modifications to both Xilinx and Intel FPGAs, which we refer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressor tree synthesis using generalized parallel counters (GPCs) is further improved with the proposed modifications. Using both the Intel adaptive logic module and the Xilinx slice at the 65nm technology node for a comparative study, it is shown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% for LUXOR+, while the delay increments are 1-6% and 3-9% respectively. We demonstrate that LUXOR can deliver an average reduction of 13-19% in logic utilization on micro-benchmarks from a variety of domains. BNN benchmarks benefit the most with an average reduction of 37-47% in logic utilization, which is due to the highly-efficient mapping of the XnorPopcount operation on our proposed LUXOR+ logic cells.

NPN classification of Boolean functions is a powerful technique used in many practical applications, including logic synthesis, technology mapping, architecture exploration, circuit restructuring, and approximate logic synthesis. Computing the canonical form of a function is the most common approach to NPN classification. Exact classification of practical functions is an open problem because there are difficult functions beyond the capability of the state-of-the-art exact algorithms, which may take several months to compute a canonical form. This article proposes a new approach to exact NPN classification, in which a series of canonical forms and the algorithms to compute them are designed together. As a result, the runtime of the exact classification for difficult functions is effectively controlled by making both representation and computation cost-aware. Experimental results show that the proposed algorithm can perform exact classification of the worst-case 16-input functions in less than 3 minutes. This indicates that, for the first time, the problem of exact classification can be effectively solved for any Boolean functions with up to 16 inputs arising in practical applications.

In-memory key-value store (IMKVS) has gained great popularity in data centers. However, big data brings great challenges in performance and power consumption because of the general-purpose Von Neumann computer architecture. Remote direct memory access (RDMA) technology supporting zero-copy networking could partly alleviate the problem but is still not efficient for KVS. To overcome this problem, we present a flexible and ultra-low-latency IMKVS system named FULL-KV, based on a CPU-FPGA heterogeneous architecture. The FPGA serves as a KVS accelerator that can bypass the CPU and implement both the network stacks and the KVS processing with a highly parallel hardware architecture. The system latency of FULL-KV can achieve as low as 1.5μs/2.2μs for the PUT/GET operation, which is 3.0x/1.5x faster than current state-of-the-art hardware-based KVS systems. Besides, FULL-KV can support 4x larger values (up to 4M bytes). Given a total Ethernet bandwidth of 20Gbps, the peak throughput of the single-node FULL-KV can reach 26.0 million key-value operations per second (Mops). In the two-node test system with a commercial Ethernet switch, the peak throughput can reach 52Mops, manifesting the system scalability and practicability.

Quantisation is a key optimisation strategy to improve the performance of floating-point deep neural network (DNN) accelerators. Digital signal processing (DSP) blocks on field-programmable gate arrays are not efficiently utilised when the accelerator precision is much lower than the DSP precision. Through three modifications to Xilinx DSP48E2 DSP blocks, we address this issue for important computations in embedded DNN accelerators, namely the standard, depth-wise, and pointwise convolutional layers. First, we propose a flexible precision, run-time decomposable multiplier architecture for CNN implementations. Second, we propose a significant upgrade to DSPDSP interconnect, providing a semi-2D low precision chaining capability which supports our low-precision multiplier. Finally, we improve data reuse via a register file which can also be configured as FIFO. Compared with the 27 × 18-bit mode in the Xilinx DSP48E2, our Precision, Interconnect, and Reuseoptimised DSP (PIR-DSP) offers a 6× improvement in multiplyaccumulate operations per DSP in the 9 × 9-bit case, 12× for 4 × 4 bits, and 24× for 2 × 2 bits. We estimate that PIR-DSP decreases the run time energy to 31/19/13% of the original value in a 9/4/2-bit MobileNet-v2 DNN implementation.

In recent years, a variety of methods for low-latency key-value store (KVS), such as remote direct memory access (RDMA), have been proposed. However, a majority of KVS systems do not support to access and query data stored in multiple versions, making them inapplicable to application scenarios like snapshot. In this paper, we present a low-latency multi-version in-memory KVS on an FPGA-CPU platform. In order to reduce latency, we store all keys into a hash table using cuckoo hashing on an FPGA board and organize each group of version-value pairs that are corresponded with the identical key into a B-tree in the host memory. The proposed architecture can perform put, get, delete, CAS, getPredecessor and range query operations within a B-tree. Every operation except range query can be completed bypassing the host CPU. The experimental results show that the average latency of get operation within a B-tree of 5 levels is less than 8?s which is at least 9x faster than other implementations with the help of CPU.

Routing architecture design is crucial in the early exploration of FPGA fabrics. In the modern unidirectional routing architectures, the signal passes through a programmable switch while turning into the channel perpendicular to the current one at the intersections, which may lead to excessive turning switches in the routing paths and cause the high latency. Most of the researches focus on the routing topology where the wire segments span in either vertical or horizontal direction. In this paper, we propose the bent routing pattern, where the bent wire segments can span in both vertical and horizontal channels without passing through any turning switch. The bent routing topology is designed to keep the regularity and symmetry, and then evaluated by the enhanced VTR. To optimize the architecture with the bent routing pattern, we develop a stochastic searching method based on the simulated annealing algorithm. The results show that the architecture with the mixture of bent wires and straight wires can achieve 9% shorter critical path delay and 11% area-delay product savings on average compared to the architecture with only straight wires.

Deep neural networks (DNNs) are widely applied to image classification tasks. Due to the fact that these models are usually vulnerable, subtle perturbations of pixels may lead to classification errors, which poses a serious threat to the success of DNN applications. Moreover, perturbations of pixels can also corrupt other pattern recognition models such as Naive Bayes (NB), Decision Tree (DT) and Random Forest (RF). In this paper, a general method is proposed to carry out targeted black-box attacks for image classification models. The proposed method can achieve targeted fool rates (TFRs) of 0.873 and 0.781 on CIFAR-10 dataset with and without the access to the training set of the target model respectively. For cross-model attacks, the proposed method can still achieve a TFR of 0.630 on CIFAR- 10. Furthermore, the proposed method is able to mount attacks for up to 100 classes on CIFAR-100 dataset with a TFR of 0.721, successfully handling 99 cases for each class. In our experiments, the proposed method shows higher performance and higher reliability than other black-box attack methods, with 0.123 greater maximum TFR and 0.602 greater minimum TFR than previous methods UPSET and ANGRI on CIFAR-10 in attacks trained on a single model.

Placement has always been the most time-consuming part of the field programmable gate array (FPGA) compilation flow. Conventional simulated annealing has been unable to keep pace with ever increasing sizes of designs and FPGA chip resources. Without utilizing information of the circuit topology, it relies on large amounts of random swap operations, which are time-costly. This paper proposes an adaptive range-based algorithm to improve the behavior of swap operations and limit the swap distances by introducing the concept of range-limiting strategy for nets. It avoids unnecessary design space exploration, and thus can converge to near-optimal solutions much more quickly. The experimental results are based on the Titan benchmarks, which contain 4K to 30K blocks, including logic array blocks, inputs and outputs, digital signal processors, and random access memories. This approach achieves$2.82\boldsymbol \times $speed up, 4.8% reduction on wire length, 4.1% improvement on critical path compared with the SA from VTR with wire length-driven optimization, and$1.78\boldsymbol \times $speed up, 10% reduction on wire length, 2% reduction on critical path with path timing-driven optimization. It also manifests better scalability on larger benchmarks.

NPN classification of Boolean functions is a powerful technique used in many logic synthesis and technology mapping tools in both standard cell and FPGA design flows. Computing the canonical form is the most common approach of Boolean function classification. This article proposes two different hybrid NPN canonical forms and a new algorithm to compute them. By exploiting symmetries under different phase assignment as well as higher-order symmetries, the search space of NPN canonical form computation is pruned and the runtime is dramatically reduced. Nevertheless, the runtime for some difficult functions remains high. Fast heuristic method can be used for such functions to compute semi-canonical forms in a reasonable time. The proposed algorithm can be adjusted to be a slow exact algorithm or a fast heuristic algorithm with lower quality. For exact NPN classification, the proposed algorithm is 40× faster than state-of-the-art. For heuristic classification, the proposed algorithm has similar performance as state-of-the-art with a possibility to trade runtime for quality.

With the continuous refinement of Deep Neural Networks (DNNs), a series of deep and complex networks such as Residual Networks (ResNets) show impressive prediction accuracy in image classification tasks. Unfortunately, the structural complexity and computational cost of residual networks make hardware implementation difficult. In this paper, we present the quantized and reconstructed deep neural network (QR-DNN) technique, which first inserts batch normalization (BN) layers in the network during training, and later removes them to facilitate efficient hardware implementation. Moreover, an accurate and efficient residual network accelerator (RNA) is presented based on QR-DNN with batch-normalization-free structures and weights represented in a logarithmic number system. RNA employs a systolic array architecture to perform shift-and-accumulate operations instead of multiplication operations. QR-DNN is shown to achieve a 1% ~ 2% improvement in accuracy over existing techniques, and RNA over previous best fixed point accelerators. An FPGA implementation on a Xilinx Zynq XC7Z045 device achieves 804.03 GOPS, 104.15 FPS and 91.41% top-5accuracyfortheResNet-50benchmark, andstate-of-the-art results are also reported for AlexNet and VGG.

Winograd algorithm is an efficient approach to alleviate the computation burden of deep CNNs. Firstly, we introduce a fast matrix algorithm to combine with Winograd algorithm to further reduce the computation complexity and adapt the Winograd algorithm to large-stride convolution with a kernel-partitioning method. Secondly, computation efficiency improvement due to the fast algorithms aggravates the off-chip communication. DRAM access of different data-flows varies significantly with different CNN patterns. Dynamic configurations of both data-flows and on-chip shared memory can reduce the DRAM access effectively. A quantitative analysis is established on the design space to guide the configurations. Finally, a reconfigurable architecture that supports three categories of data-flows is presented. For evaluation, VGGNet16, AlexNet and ResNet50 are implemented respectively which can achieve the state-of-art DSP efficiency. Overall performance of 685.6GOP/s, 1250GOP/s and 507GOP/s for AlexNet, VGGNet16 and ResNet50 respectively on ZC706 platform and better energy efficiency are achieved compared with representative prior works.

NPN classification of Boolean functions is a powerful technique used in many logic synthesis and technology mapping tools in FPGA design flows. Computing the canonical form of a function is the most common approach of Boolean function classification. In this paper, a novel algorithm for computing NPN canonical form is proposed. By exploiting symmetries under different phase assignments and higher-order symmetries of Boolean functions, the search space of NPN canonical form computation is pruned and the runtime is dramatically reduced. The algorithm can be adjusted to be a slow exact algorithm or a fast heuristic algorithm with lower quality. For exact classification, the proposed algorithm achieves a 30× speedup compared to a state-of-the-art algorithm. For heuristic classification, the proposed algorithm has similar performance as the state-of-the-art algorithm with a possibility to trade runtime for quality.

In-memory key-value store (KVS) is critical infrastructure in data centers and is facing challenges in performance and power consumption with the development of the big data technology, which mainly results from the low efficiency of the multi-level memory hierarchy of the CPU-based system. Remote direct memory access (RDMA) technology partly alleviates the problems, but it is still not efficient for KVS, especially for the PUT operation. In this paper, we present an ultra-low-latency and flexible in-memory KVS system based on the CPU-FPGA heterogeneous architecture, which leverages FPGA to serve as a KVS accelerator. We design a highly parallel accelerator architecture with several novel techniques, including memory pre-allocation, fragmentation processing, and decoupling design, to achieve ultra-low latency, high flexibility, efficiency, and scalability. The system workload can scale up with the storage capacity due to the decoupling design which stores the hash table in onboard DRAM memory and values in the host memory. For each KVS operation, at most one PCIe DMA is needed, which achieves high efficiency. Compared with current hardware-based KVS systems, the proposed one is more flexible, where the supported value range is 4x wider (from 1 byte to 4M bytes). In 10Gbps Ethernet, the peak throughput of the system can reach 13.6 million key-value operations per second (Mops), achieving nearly full utilization of the Ethernet bandwidth. The system latency can achieve as low as 1.2us for the PUT operation and 1.7us for the GET operation, which is 3.8x and 2.0x faster respectively than current state-of-the-art KVS systems.

Due to the fact that FPGA on-chip memory capacity increases significantly, the feature maps and weights of convolutional layers can be stored on chip, which can reduce the data movement between on-chip memory and off-chip memory. Hence, the bottleneck can shift from the bandwidth to the computing resources in convolutional layers, which will improve the performance dramatically. Under this circumstance, this paper quantitatively analyzes how to design the hardware architecture based on the roofline model to optimize the performance under the constraints of available on-chip computing resources and propose an efficient architecture. Our accelerator is implemented on Xilinx UltraScale+ FPGA with the performance of 9.39 TOPS and 6.86 TOPS for 8-bit data width with 100MHz main frequency and 400MHz DSP frequency on ResNet-50 and AlexNet, which outperforms the existing FPGA-based CNN accelerator.

Key-value store (KVS) systems are playing important roles as the caches of database to improve the data access efficiency. In this paper, we propose general architectures of KVS systems based on field programmable gate arrays (FPGAs) which can adapt to different application scenarios. Data hazards introduced by the pipeline are fully handled to improve the throughput. The batch operation is proposed to support the variable-length key-value pairs. The memory address management system reduces CPU load further by managing memory addresses on hardware. We implement and evaluate our KVS systems on VC709 evaluation board targeting throughput, latency and capacity respectively. The ultra-low latency KVS system can achieve 160 ns latency and about 155 million request per second (MRPS) to retrieve 96-bit values with 96-bit keys. The ultra-high throughput KVS system can achieve about 200 ns latency and 200 MRPS throughput to retrieve the same size key-value pairs. The ultra-capacity KVS system retrieves 64-byte values with 12-byte keys, serving a maximum request rate of more than 35 MRPS with latency less than 500 ns.

Convolutional Neural Networks (CNNs) can achieve high classification accuracy while they require complex computation. Binarized Neural Networks (BNNs) with binarized weights and activations can simplify computation but suffer from obvious accuracy loss. In this paper, low bit-width CNNs, BNNs and standard CNNs are compared to show that low bit-width CNNs is better suited for embedded systems. An architecture based on the two-stage arithmetic unit (TSAU) as the basic processing element is proposed to process each layer iteratively for low bit-width CNN accelerators. Then the DoReFa-Net which is trained with weights and activations represented in 1 bit and 2 bits respectively is implemented on Zynq XC7Z020 FPGA with a 410.2 GOPS performance. The accelerator can meet the real-time requirement of embedded applications with a 106 FPS throughput and a 73.1% top-5 accuracy on the ImageNet dataset. The accelerator outperforms existing FPGA-based CNN accelerators in the tradeoff among accuracy, energy and resource efficiency.

Tandem mass spectrometry has been a main method for protein identification. X!Tandem, a widely used database search engine, may spend hours or days accomplishing a certain searching task due to the increased search space, which generates urgent demands for computationally efficient database searching. Profiling analysis indicates that it takes X!Tandem about 70%-90% of the total time to conduct the scoring process. The scoring process is composed of fragment ion generation and score generation. This paper proposes a scalable hardware design to speed up the scoring process of X!Tandem that exploits the flexibility of Field Programmable Gate Arrays (FPGAs). The hardware implementation of the scoring process that instantiates 1 fragment ion generation module and 6 score generation modules running on a Xilinx Virtex-7 XC7VX690T FPGA can achieve a 26 times speedup, compared with X!Tandem software implementation running on a 2.5GHz Intel i7-4870 processor with 16 GB memory, whilst fragment ion generation can achieve a 67 times speedup and score generation can achieve a 17 times speedup. Besides, the scalability of score generation modules is linear and outperforms previous parallel approaches.

This paper presents a scalable hybrid architecture for high performance data-parallel applications on tightly coupled shared-memory CPU-FPGA systems such as the Xilinx Zynq SoC. The aims of the proposed architecture are: 1)to simplify the development of hardware acceleration for dataparallel applications; 2)to reach the performance limit caused by memory access and/or hardware resource available on an FPGA; 3)to reduce the overhead caused by task scheduling and device drivers. The proposed architecture can be used as a generic template to implement data-parallel applications. Each task in an application is mapped to one hardware accelerator, which is called “kernel”. Several identical instances of each hardware kernel execute concurrently to provide parallelism. By deploying the maximum number of instances of the hardware kernel, we make full use of the bandwidth of memory access and the resources available on the FPGA. In order to improve performance further, task scheduling and device drivers are implemented as a hardware scheduler called DmaScheduler on FPGA hardware. Experimental results show 2.93x-51.25x speedup on Zynq FPGA for applications of image processing, Black Scholes option pricing, matrix multiplication and clustering algorithm, compared with existing FPGA implementations.

Placement has always been the most time-consuming part in the FPGA compilation flow. Traditional simulated annealing has been unable to keep pace with ever increasing sizes of designs and FPGA chip resources. Without utilizing information of the circuit topology, it relies on large amounts of random swap operations, which are time-costly. This paper proposes a range-based algorithm to improve the behavior of swap operations and limit the swap distances by introducing the concept of range limiting for nets. It avoids unnecessary design space exploration, and thus can converge to near-optimal solutions much more quickly. The Titan benchmarks we have tested on contains 4K to 30K blocks, which include LABs, IOs, DSPs and RAMs. This approach achieves 2.05X speed up on average compared with the SA from VTR while preserving the placement quality of both the wire length and critical path. It also manifests better scalability towards larger benchmarks.

As the density of field-programmable gate arrays continues to increase, the size of configuration bitstreams grows accordingly. Compression techniques can reduce memory size and save external memory bandwidth. To accelerate the configuration process and reduce the software startup time, four open-source lossless compression decoders developed using high-level synthesis techniques are presented. Moreover, in order to balance the objectives of compression ratio, decompression throughput, and hardware resource overhead, various improvements and optimizations are proposed. Full bitstreams and software binaries have been collected as a benchmark, and 33 partial bitstreams have also been developed and integrated into the benchmark. Evaluations of the synthesizable compression decoders are demonstrated on a Xilinx ZC706 board, showing higher decompression throughput than those of the existing lossless compression decoders using our benchmark. The proposed decoders can reduce software startup time by up to 31.23% in embedded systems and 69.83% reduction of reconfiguration time for partial reconfigurable systems.

With the development of wireless communication technology, 5G will develop into a new generation of wireless mobile communication systems. MIMO (multiple-input multiple-output) technology is expected to be one of the key technologies in the field of 5G wireless communications. In this paper, 4 pairs of microstrip MIMO conformal antennas of 35 GHz have been designed. Eight-element microstrip Taylor antenna array with series-feeding not only achieves the deviation of the main lobe of the pattern but also increases the bandwidth of the antenna array and reduces sidelobe. MIMO antennas have been fabricated and measured. Measurement results match the simulation results well. The return loss of the antenna at 35 GHz is better than 20 dB, the first sidelobe level is −16 dB, and the angle between the main lobe and the plane of array is 60°.

This paper presents a new type of coarse-grained reconfigurable architecture (CGRA) for the object inference domain in machine learning. The proposed CGRA is optimized for stream processing and a correspondent programming model called dual-track model is proposed. The CGRA is realized in Verilog HDL and implemented in SMIC 55 nm process, with the footprint of 3.79 mm2and consuming 1.79 W at 500 MHz. To evaluate the performance, eight machine-learning algorithms including HOG, CNN, k-means, PCA, SPM, linear-SVM, Softmax and Joint-Bayesian are selected as benchmarks. These algorithms cover a general machine learning flow in object inference domain: feature extraction, feature selection and inference. The experimental results show that the proposed CGRA can gain 1443× average energy efficiency comparing to the Intel i7-3770 CPU and 7.82× energy efficiency comparing to a high performance FPGA solution [19].

In recent years, convolutional neural networks (CNNs) based machine learning algorithms have been widely applied in computer vision applications. However, for large-scale CNNs, the computation-intensive, memory-intensive and resource-consuming features have brought many challenges to CNN implementations. This work proposes an end-to-end FPGA-based CNN accelerator with all the layers mapped on one chip so that different layers can work concurrently in a pipelined structure to increase the throughput. A methodology which can find the optimized parallelism strategy for each layer is proposed to achieve high throughput and high resource utilization. In addition, a batch-based computing method is implemented and applied on fully connected layers (FC layers) to increase the memory bandwidth utilization due to the memory-intensive feature. Further, by applying two different computing patterns on FC layers, the required on-chip buffers can be reduced significantly. As a case study, a state-of-the-art large-scale CNN, AlexNet, is implemented on Xilinx VC709. It can achieve a peak performance of 565.94 GOP/s and 391 FPS under 156MHz clock frequency which outperforms previous approaches.

Key-value stores (KVS) become critical in many applications because of the data explosion recently. There is a strong demand to improve the throughput and reduce the latency for KVS. FPGA-based parallel architecture can bring excellent performance and power efficiency. Cuckoo hashing has proven to be an efficient approach to implement KVS with good memory utilization and constant worst case access time. In this paper, an FPGA-based KVS implementation is proposed based on Cuckoo hashing, with a decoupled storage to achieve 81.7% memory utilization, and a pipeline scheme to achieve high performance. The latency of insert, search and delete operations is only 40 ns. And the throughput for search and delete can be 200 million requests per second (MRPS) which is 5× faster than [1]. Even when the load factor becomes 0.9, the throughput for insert can still achieve 147 MRPS.

This paper introduces cycle-reconfigurable modules that enhance FPGA architectures with efficient support for dynamic data accesses: data accesses with accessed data size and location known only at runtime. The proposed module adopts new reconfiguration strategies based on dynamic FIFOs, dynamic caches, and dynamic shared memories to significantly reduce configuration generation and routing complexity. We develop a prototype FPGA chip with the proposed cycle-reconfigurable module in the SMIC 130-nm technology. The integrated module takes less than the chip area of 39 CLBs, and reconfigures thousands of runtime connections in 1.2 ns. Applications for large-scale sorting, sparse matrix-vector multiplication, and Memcached are developed. The proposed modules enable 1.4 and 11 times reduction in area-delay product compared with those applications mapped to previous architectures and conventional FPGAs.

In this demonstration, we develop a moving object extraction and classification system based on a heterogeneous acceleration platform that consists of a local Zynq terminal and FPGA clusters on the IBM SuperVessel cloud. Extraction of the moving object from the streaming video input is offloaded to the Zynq terminal, while the classification is executed on the cloud. FPGA high level synthesis and Xilinx SDSoC Environment are applied to develop the extraction part of the system. In evaluation, the extraction and classification parts of our system achieve performance of 30 fps and 1 fps respectively for 1080P streaming video input. This demonstration displays a feasible framework for the hardware acceleration of computer vision applications and a possible job division between the terminal and the cloud.

Deformable Part Model (DPM) is one of the best algorithms for image-based object detection. However, the high computation intensity leads to relatively long detecting time. Even with the powerful CPU or GPU computing system, it is still too slow for practical applications. To solve this problem, this paper proposes a high performance DPM accelerator based on FPGA, where a dedicated JPEG decoder is integrated to process the images with the 1080p JPEG format. Pipelined architecture and data reuse strategies are developed to achieve the high throughput and energy efficiency. The proposed accelerator can process input images with 22 fps at the frequency of 156MHz on Xilinx VC709 board, which outperforms previous approaches.

This paper proposes UniStream, a unified stream architecture based on point-to-point stream channels combining both bitstream configuration and data stream processing. In addition, unified APIs are provided to support bitstream configuration and data stream processing, as well as the stream interconnect. A cost model is also presented for the overhead on the stream interconnect, hardware task configuration and data stream processing at system level, which can be used during the early stage of development. The flexibility and high efficiency of UniStream are demonstrated on Xilinx Virtex-5 and Virtex-6 FPGAs. Experimental results on bitstream configuration/ read-back, data encryption/decryption and Discrete Cosine Transformation show that performance can be significantly improved with different stream modes.

Due to the technology scaling, the reconfigurable SoCs built on SRAM-based FPGAs become more susceptible to radiation and aging effects. This paper proposes an adaptive cross-layer fault recovery solution based on hardware/software co-design for reconfigurable SoCs. By pyramidal structure design and cross-layer adaptivity, our solution gives both consideration to hardware circuit integrity at the hardware level and application operating normality at the software level with reduced correction cost. The experiment result shows that the proposed solution can efficiently increase the system reliability and decrease the correction cost.

Sparse Matrix-Vector Multiplication (SpMxV) algorithms suffer heavy performance penalties due to irregular memory accesses. In this paper, we introduce a novel compressed element storage (CES) format, in which the additional data structures for indexing are abandoned, and each location associated with the non-zero element of the matrix is now indicated by the name of a variable multiplied by the corresponding element of the vector. To ensure fastest access and parallel access without data hazards, on-chip registers are used exclusively to replace the BRAM or off-chip DRAM/SRAM to hold all the SpMxV data. On-chip DSP resources are fully utilized so as to ensure a maximum number of multipliers concurrently working.

This paper presents a parameterized system-level design framework, which enables rapid and powerful research for hybrid multicore architecture exploration and hardware/software co-design. The framework comprises the component-based hardware design and application compiler, which make it easy for a designer to build stream-oriented applications with FPGA-based hybrid multicore architectures. The high modularity and parameterization of the framework supports fast multicore architecture exploration of different topologies, routing schemes, processor types, customized hardware processing units and memory system organizations. The compiler tool chain is used to map C/C++ based applications onto the soft processing units. Experimental results targeting the JPEG encoding application demonstrate the feasibility and performance improvement of this framework.

In order to find a sensitive and stable auscultatory method, recognition algorithm for human-voice matching with 25 patterns for 25Yin, a pattern library with 25 sounds as standard patterns was established in this manuscript. Furthermore, Mel Frequency Cepstrum Coefficient (MFCC) was applied to analyse for sampled sound and then the algorithm of Support Vector Machine (SVM) was used to match the sampled sound, which had been dipt the baseline signal and the signal at the part of consonants in each single pronunciation during voice sampling, with every sound in the pattern library. A table had been listed with 25 nomenclature for 25 Yin described in HDNJ and related to the code-named (CN) of the wave sound from BMYZ. The recognition algorithm based on MFCC plus SVMto match human-voice and the pattern library with 25 sounds offered a well-accuracy well-precision and potential technique to recognize different individuals according to the classic theory.

A Quantum FPGA (QFPGA) architecture is presented for programmable quantum computing, which is a hybrid architecture combining the advantages of the measurement-based quantum computation and the qubus system. QFPGA consists of Quantum Logic Blocks (QLBs) and Quantum Routing Channels (QRCs). The QLB is used to realize a small quantum logic while the QRC is to combine them properly for larger logic realization. There are two types of buses in QFPGA, the local bus in the QLB and the global bus in the QRC, which are to generate the cluster states and general multiqubit rotations around the z axis respectively. However for some applications such as Grover's algorithm and n-qubit quantum Fourier transform, one QLB can be configured for four-qubit phase shift module and four-qubit quantum Fourier transform respectively.

This paper proposes a high performance hardware architecture of Speeded Up Robust Features (SURF) algorithm based on OpenSURF. In order to achieve high processing frame rate, the hardware architecture is designed with several characteristics. Firstly, a sliding window method is proposed to extract feature points in parallel at selected scale levels. As a result, the time cost in feature extraction can be greatly reduced. Secondly, data reuse strategy is proposed in orientation generation and descriptor generation to reduce the memory access times. In this way, 3.87x and 2.25X speedup are achieved respectively. Thirdly, the integral image is segmented to buffer in different memory blocks in order to support multiple data accessing in one clock cycle, which will further reduce the whole calculating time of our implementation. The hardware architecture is implemented on an XC6VSX475T FPGA with 156 MHz and its maximal frame rate for VGA format image can reach 356 frames per second (fps), which is 6.25 times frame rate of OpenSURF running on a server with a Xeon 5650 processor, and 6 times the reported frame rate of the recent implementation on three Vritex4 FPGAs [8].

This paper proposes a fast algorithm for Boolean matching of completely specified Boolean functions. The algorithm is based on the NPN classification and can be applied on-the-fly to millions of small practical functions appearing in industrial designs, leading to runtime and memory reduction in logic synthesis and technology mapping. The algorithm is conceptually simpler, faster, and more scalable than previous work.

In this paper, a high-performance match engine for content-based image retrieval is proposed. Highly customized floating-point(FP) units are designed, to provide the dynamic range and precision of standard FP units, but with considerably less area than standard FP units. Match calculation arrays with various architectures and scales are designed and evaluated. An CBIR system is built on a 12-FPGA cluster. Inter-FPGA connections are based on standard 10-Gigabyte Ethernet. The whole FPGA cluster can compare a query image against 150 million library images within 10 seconds, basing on detailed local features. Compared with the Intel Xeon 5650 server based solution, our implementation is 11.35 times faster and 34.81 times more power efficient.

Algorithms such as Bag of Words and Simhash have been widely used in image recognition. To achieve better performance as well as energy-efficiency, a hardware implementation of these two algorithms is proposed in this paper. To the best of our knowledge, it is the first time that these algorithms have been implemented on hardware for image recognition purpose. The proposed implementation is able to generate a fingerprint of an image and find the closest match in the database accurately. It is implemented on Xilinx's Virtex-6 SX475T FPGA. Tradeoffs between high performance and low hardware overhead are obtained through proper parallelization. The experimental result shows that the proposed implementation can process 1,018 images per second, approximately 17.8x faster than software on Intel's 12-thread Xeon X5650 processor. On the other hand, the power consumption is 0.35x compared to software-based implementation. Thus, the overall advantage in energy-efficiency is as much as 46x. The proposed architecture is scalable, and is able to meet various requirements of image recognition.

Partially reconfigurable systems are promising computing platforms for streaming applications, which demand both hardware efficiency and reconfigurable flexibility. To realize the full potential of these systems, a streaming-based partially reconfigurable architecture and unified software/hardware multithreaded programming model (SPREAD) is presented in this paper. SPREAD is a reconfigurable architecture with a unified software/hardware thread interface and high throughput point-to-point streaming structure. It supports dynamic computing resource allocation, runtime software/hardware switching, and streaming-based multithreaded management at the operating system level. SPREAD is designed to provide programmers of streaming applications with a unified view of threads, allowing them to exploit thread, data, and pipeline parallelism; it enhances hardware efficiency while simplifying the development of streaming applications for partially reconfigurable systems. Experimental results targeting cryptography applications demonstrate the feasibility and superior performance of SPREAD. Moreover, the parallelized Advanced Encryption Standard (AES), Data Encryption Standard (DES), and Triple DES (3DES) hardware threads on field-programmable gate arrays show 1.61-4.59 times higher power efficiency than their implementations on state-of-the-art graphics processing units.

As a promising computing platform for stream processing, partially reconfigurable systems have shown their hardware efficiency and reconfiguration flexibility. This paper presents a partially reconfigurable architecture supporting hardware threads. It gives a unified software/hardware thread interface and high throughput point-to-point streaming structure. Dynamic computing resource allocation and streaming-based multi-threaded management are also provided at operating system level. It is easy for programmers to exploit the inherent thread, data and pipeline parallelism in a unified view of threads, enhancing hardware efficiency while improving productivity. The experimental results on a cryptography application demonstrate the feasibility and superior performance. Moreover, the parallelized AES, DES and 3DES hardware threads on field-programmable gate arrays show 1.61-4.59 times higher power efficiency than their implementations on state-of-the-art graphics processing units.

Deriving a circuit for a Boolean function or improving an available circuit are typical tasks solved by logic synthesis. Numerous algorithms in this area have been proposed and implemented over the last 50 years. This paper presents a "lazy" approach to logic synthesis based on the following observations: (a) optimal or near-optimal circuits for many practical functions are already derived by the tools, making it unnecessary to implement new algorithms or even run the old ones repeatedly; (b) larger circuits are composed of smaller ones, which are often isomorphic up to a permutation/negation of inputs/outputs. Experiments confirm these observations. Moreover, a case-study shows that logic level minimization using lazy man's synthesis improves delay after LUT mapping into 4- and 6-input LUTs, compared to earlier work on high-effort delay optimization.

This paper presents a phenology-preserving filtering method as a significant improvement to the standard changing-weight filter method to reduce noise in NDVI time series. Specifically it introduces two new features: (1) replacing the changing-weight filter with a 3-point Gaussian filter to improve the computing efficiency; and (2) introducing a multi-year average NDVI time series to remove the false local minima points. This phenology-preserving filtering method was tested at 178 test points for 15 land cover types and 6 test regions around the world using the 250 m 16-day MODIS NDVI product. The results were evaluated in comparison with the original changing-weight filter and other three popular filtering methods. The visual and quantitative analyses demonstrate that the phenology-preserving filtering method can effectively reduce noise and preserve the integrity of the time series with a high computing efficiency.

Taking the standard vegetation spectral library data and the hyperspectral Hyperion remote sensing image, five similarity measure methods (i.e., Euclidean distance, spectral information divergence, spectral angle cosine, spectral correlation coefficient and spectral angle cosine-Euclidean distance) are comprehensively evaluated under a unified testing framework. The results indicate that the spectral angle cosine-Euclidean distance method demonstrates the most superior ability to distinguish various land cover types among five methods because it fully utilizes both the spectral amplitude and shape feature in the hyperspectral data. A combination of the spectral amplitude-sensitive method and the shape-sensitive method will effectively improve the identification accuracy of different land cover types. These evaluation results can be used to guide the selection of an optimal similarity measure method for automatic classification with hyperspectral data.

This paper evaluated the extraction rate and accuracy of 5 phenology extracting method, taking the vegetation phenological metrics derived from the net ecosystem carbon exchange (NEE) data of 72 flux towers in North America as the reference data. The results indicated that the local midpoint method achieved the highest extraction rate and accuracy. Better performance was observed for the moving average method and the polynomial function fitting method. However, the extraction rate and accuracy of the moving average method were sensitive to the moving window size. The global threshold method performed quite poor. The phenological metrics extracted with the piecewise Logistic function fitting method had a large systematic discrepancy with the NEE derived phenological metrics but there was a strong correlation between them, which indicated that the vegetation phenological metrics extracted with the piecewise Logistic function fitting method can reflect the temporal and spatial variation of vegetation phenology.

Time-series data of normalized difference vegetation index (NDVI), derived from satellite sensors, can be used to support land-cover change detection and phenological interpretations, but further analysis and applications are hindered by residual noise in the data. As an alternative to a number of existing algorithms developed to compensate for such noise, we develop a simple but computationally efficient method (which we call the changing-weight filter method) to reconstruct a high-quality NDVI time series. The new algorithm consists of two major procedures: (1) detecting the local maximum/minimum points in a growth cycle along an NDVI temporal profile based on a mathematical morphology algorithm and a rule-based decision process and (2) filtering an NDVI time series with a three-point changing-weight filter. This method is tested at 470 test points for 55 vegetation types and a test region in China using a 250-m 16-day Moderate Resolution Imaging Spectroradiometer (MODIS) NDVI product. Comparing our results to those of three other well-known methods-asymmetric Gaussian function fitting, double logistic function fitting, and Savitzky-Golay filtering-the new method has many of the advantages of existing methods, while in some cases, the changing-weight filter method more effectively preserves the curve shape as well as the timing and the amplitude of the local maxima/minima in the NDVI time series for a broad range of phenologies. Moreover, the response of the filtering algorithm is relatively insensitive to the exact values of its design parameters, making the new method more flexible and effective in adjusting to fit a variety of classes of NDVI time series.

This paper proposes a new parameterized dynamic thermal modeling algorithm for emerging thermal-aware design and optimization for high-performance microprocessor design at architecture and package levels. Compared with existing behavioral thermal modeling algorithms, the proposed method can build the compact models from more general transient power and temperature waveforms used as training data. Such an approach can make the modeling process much easier and less restrictive than before and, thus, more amenable for practical measured data. The new method, called ParThermSID, consists of two steps. First, the response surface method based on second-order polynomials is applied to build the parameterized models at each time point for all of the given sampling nodes in the parameter space. Second, an improved subspace system identification method, called ThermSID, is employed to build the discrete state space models, by construction of the Hankel matrix and state space realization, for each time-varying coefficient of the polynomials generated in the first step. To overcome the overfitting problems of the subspace method, the new method employs an overfitting mitigation technique to improve model accuracy and predictive ability. Experimental results on a practical quad-core microprocessor show that the generated parameterized thermal model matches the given data very well. The compact models generated by ParThermSID also offer two orders of magnitude speedup over the commercial thermal analysis tool FloTHERM on the given example. The results also show that ThermSID is more accurate than the existing ThermPOF method.

This paper presents a parallel and incremental solver for stochastic capacitance extraction. The random geometrical variation is described by stochastic geometrical moments, which lead to a densely augmented system equation. To efficiently extract the capacitance and solve the system equation, a parallel fast-multipole-method (FMM) is developed in the framework of stochastic geometrical moments. This can efficiently estimate the stochastic potential interaction and its matrix-vector product (MVP) with charge. Moreover, a generalized minimal residual (GMRES) method with incremental update is developed to calculate both the nominal value and the variance. Our overall extraction show is called piCAP. A number of experiments show that piCAP efficiently handles a large-scale on-chip capacitance extraction with variations. Specifically, a parallel MVP in piCAP is up 3 × to faster than a serial MVP, and an incremental GMRES in piCAP is up to 15× faster than non-incremental GMRES methods.

Boolean matching is one of the most important fundamental algorithms in FPGA synthesis and architecture evaluations. However, existing Boolean matchers for FPGAs, even with numerous improvements, are still not scalable to complex PLBs and large circuits. This paper aims to improve the efficiency of Boolean matching using lookup tables implemented by Bloom filters, which can store terabyte-lookup tables with a desktop PC. The key improvement is to efficiently prune a large set of non-implementable functions use the Bloom filter. Using the area-oriented re-synthesis as an application, the experiments on a broad selection of benchmark sets show that the re-synthesis with our improved Boolean matcher is 18X faster than the one with an optimized SAT-based Boolean matcher, while preserving the quality of the re-synthesizer.

This paper explores the FPGA routing architecture based on a new concept of “general switch box (GSB)” to improve the performance of FPGA. Compared with the existing CB/SB routing architecture and CS-box architecture, the proposed GSB architecture has much larger exploration space. Experimental results with MCNC benchmark circuits show that the performance of FPGAs with GSB is about 24.3% better than the CB/SB architecture with the same segment distribution in terms of product of channel width and delay using 0.17% less routing switches for the single wire length. For the two types of wire segments, we propose an architecture with 13.3% performance improvement at the cost of about 0.8% increase in switch number compared to the single wire length GSB architecture.

Software as a Service (SaaS) 1.0 signifcantly lowers the infrastructure and maintenance cost and increases the accessibility of the software by hosting software via the web. Compared with SaaS 1.0, SaaS 2.0 is more flexible since it leverages software tools from both server and client sides with closer interaction between them. The SaaS 2.0 paradigm provides new opportunities and challenges for EDA. In this paper, we take Boolean matching, one of the core sub algorithms in logic synthesis for field programmable gate arrays (FPGAs), as a case study. We investigate the advantages and challenges of implementing a scalable EDA algorithm under SaaS 2.0 paradigm from a technical perspective. We propose SaaS-BM, a new Boolean matching algorithm customized to take full advantage of the cloud while addressing concerns such as security and the internet bandwidth limit. Extensive experiments are performed under a networked environment with concurrent accesses. Integrated into a post-mapping re-synthesis algorithm minimizing area, the proposed SaaS-BM is 863X times faster than state-of-the-art SAT-based Boolean matching with 0.5% area overhead. Compared with a recent Bloom Filter-based Boolean matching algorithm, our proposed SaaS-BM is 53X times faster on large circuits with no area overhead.

The Moderate Resolution Imaging Spectroradiometer (MODIS) sensor is currently being operated on both Terra and Aqua spacecrafts. MODIS uses 36 bands arranged in four focal plane assemblies (FPAs) - visible, near infrared, short- and middle-wavelength infrared, and long-wavelength infrared. Misregistrations between spectral bands and FPAs and changes of spatial characterization on-orbit could impact the quality of science data products generated with multiple bands located on different FPAs. In this paper, an approach is presented to compute the MODIS band-to-band registration (BBR) using ground measurements. A special ground scene with unique features is selected to calculate the spatial registration along-scan and along-track. The monthly and yearly spatial deviations are calculated for the bands of both Terra and Aqua MODIS except for some ocean bands, cloud bands, and the Aqua MODIS band 6. The comparison with results derived from the spectroradiometric calibration assembly, a device operated on-orbit to track the BBR shift between any two of the spectral bands, generally shows good agreement. The measured differences between these two approaches are typically less than 100 m in the scan direction and 200 m in the track direction. This approach can provide more frequent characterization of the MODIS BBR and is extremely useful for other sensors that do not have an onboard spatial characterization device.

Sand and dust storms (SDSs), which present environmental risks and affect the regional climate, have been worsened in the East Asian regions over the last decade. Monitoring SDS from space using satellite remote sensing (RS) has become one of the most important issues in this field. At present, satellite RS of SDS is limited to using true-color images or aerosol optical thickness (AOT), or a new algorithm called "Deep Blue". Using current existing approaches makes it difficult to identify SDS from clouds. The authors have detected SDS by combining Terra and Aqua Moderate Resolution Imaging Spectroradiometer (MODIS) solar reflectance band (SRB) measurements. Based on the dust spectral characteristic, this letter proposes a normalized difference dust index (NDDI) using MODIS reflectance measurements and applies it to the Asian SDS cases. The simple NDDI index is found to be able to identify SDS and clouds easily. The results suggest that NDDI could be used to detect SDS over bright surfaces where the MODIS AOT product is not available

The Moderate Resolution Imaging Spectroradiometer (MODIS) is a key research instrument for the NASA Earth Observing System (EOS) mission. It was successfully launched onboard the Terra satellite in December 1999 and Aqua satellite in May 2002. Both MODIS instruments have been working well except that 15 of the 20 detectors in Aqua MODIS band 6 (1.628-1.652 μm) are either nonfunctional or noisy. The striping in Aqua MODIS band 6 caused by its nonfunctional or noisy detectors has been a serious problem for MODIS snow products, which use band 6 primarily for snow detection. MODIS scientists have been using Aqua MODIS band 7 (2.105-2.155 μm) instead of band 6 for computing the normalized difference snow index to continue detecting global snow coverage. The main objective of this letter is to retrieve Aqua MODIS band 6 using other bands based on their relationships in Terra MODIS. The band retrieval approach proposed in this letter is also very useful for the next generation of MODIS sensor-the Visible/Infrared Imager/Radiometer Suite (VIIRS) band M10 proxy data generation. Such proxy data can support the VIIRS prelaunch end-to-end testing, postlaunch calibration/validation, and data quality checking.

Calibration and validation (Cal/Val) toolkits are very critical for both satellite pre-launch end-to-end testing and post-launch real data quality check-out. In this paper, we present a AIRS-MODIS-VIIRS band mapping toolkit, which is designed for cross comparison and cross calibration of AIRS-MODIS-VIIRS thermal infrared bands based on the band-mapping approach we proposed. The main functionalities of this toolkit include spatial match-up between AIRS and MODIS foot prints, spectral simulation of VIIRS and MODIS thermal infrared bands with AIRS measurements, visual and statistical analyses among VIIRS, MODIS and AIRS thermal infrared bands for stratified scene characteristics, channels and scan angles. It also provides basic data manipulation and file format conversion capabilities. This toolkit can provide supports for VIIRS calibration and can be further enhanced into a NPOESS/NPP post-launch toolkit for real-time cross-instrument calibration and data quality check.