This work discusses the synthesis and design methodology of high-order and frequency-tunable low-pass active-R filter architectures for multi-standard wireless applications. Active-R filters use the inherent integrator-like behavior of amplifiers to realize their frequency response. The main advantages of this type of filter are high-frequency performance and a low integrated area. Active-R filters only need the Miller capacitor used in internally compensated amplifiers. In this work, amplifiers with configurable unity-gain frequencies enable the continuous tuning of active-R filters. Three different filter architectures realize a fifth-order Butterworth prototype tunable in the 1-50 MHz frequency range. These filters are designed, fabricated, and tested using the TSMC 0.18 μm process. Each fifth-order filter consumes power in the range 7.45 mW to 9.38 mW from a 1.8 V supply and has an integrated area ≤ 0.33 mm2. Compared with state-of-the-art active filters, the filters presented in this work have the largest tuning range without linearity degradation and the smallest area per tuning range ratio. Also, the measured filters show a competitive FoM 153.3 dB/J when operating at high frequencies.

An energy harvesting (EH) system is proposed to extract energy from a centimeter-scale electromagnetic (EM) micro wind turbine. To improve the end-to-end efficiency, an autonomous and self-biased active rectifier is employed. A hysteresis-controlled boost converter is designed with self-zero-current-switching calibrations, which achieves a peak DC-DC efficiency of 93.3% with a maximum efficiency improvement of 12.7%. In addition, a novel frequency-to-amplitude conversion (FAC) maximum power point tracking (MPPT) method is proposed for a cycle-to-cycle MPPT. In measurements, the proposed FAC MPPT requires no more than three cycles to locate the maximum power point (MPP) in abrupt frequency changes, with an 80% tracking accuracy in the first turbine cycle. In wind-field testing, the EH system starts to track the MPP one cycle after start-up at 2.0 V. In the steady-state, the EH system maintains its cycle-to-cycle MPP under different wind conditions. In wind-field testing for wind speeds from 1.0 to 5.0 m/s, the peak MPPT accuracy is 99.27%, with an MPPT efficiency of 99.85%. The extracted power is from 0.1 to 8 mW with a peak end-to-end efficiency of 88.2%. Compared to a full-bridge rectifier, a 630% energy extraction gain is measured at a low wind speed of 1.2 m/s. To the best of the authors' knowledge, this is the first IC prototype for a cm-scale EM wind turbine EH to achieve a cycle-to-cycle MPPT with the highest reported MPPT efficiency.

With the growing performance and wide application of deep neural networks (DNNs), recent years have seen enormous efforts on DNN accelerator hardware design for platforms from mobile devices to data centers. The systolic array has been a popular architectural choice for many proposed DNN accelerators with hundreds to thousands of processing elements (PEs) for parallel computing. Systolic array-based DNN accelerators for datacenter applications have high power consumption and nonuniform workload distribution, which makes power delivery network (PDN) design challenging. Server-class multicore processors have benefited from distributed on-chip voltage regulation and heterogeneous voltage regulation (HVR) for improving energy efficiency while guaranteeing power delivery integrity. This paper presents the first work on HVR-based PDN architecture and control for systolic array-based DNN accelerators. We propose to employ a PDN architecture comprising heterogeneous on-chip and off-chip voltage regulators and multiple power domains. By analyzing patterns of typical DNN workloads via a modeling framework, we propose a DNN workload-aware dynamic PDN control policy to maximize system energy efficiency while ensuring power integrity. We demonstrate significant energy efficiency improvements brought by the proposed PDN architecture, dynamic control, and power gating, which lead to a more than five-fold reduction of leakage energy and PDN energy overhead for systolic array DNN accelerators.

In this work, a harmonic-canceling synthesizer for Built-In Self-Test (BIST) applications is presented. The main contribution is the implementation of the required irrational tap coefficients by using integer numbers in a recursive approach without any calibration scheme. A coefficient generator that exploits properties of skew-circulant matrices and relaxes the trade-off between output linearity and coefficients mismatch is proposed. The cascade of Harmonic-Canceling Filters (HCFs) allows to filter out up to the 47th harmonic of the input square-wave. Also, a band-pass HCF that enables the selection of its input's 1st or 5th harmonic is presented. The system is fabricated in 180nm CMOS technology. Measurement results show a maximum 66 dBc Spurious-Free Dynamic Range (SFDR) and output frequencies ranging from 0.8 MHz to 100 MHz.

Analog/RF performance locking techniques insert configurable components to obfuscate the biasing or the design parameters of the secured analog block. The locked circuit meets the specifications only under a specific configuration decided by the correct common key, shared by all chip instances of the same design. Key provisioning enables the design of distinct user keys for individual chip instances. This area has received little research attention, and a naive approach yields large area overhead when increasing the key size. We propose a new approach based on a Schmitt trigger (ST) circuit with configurable hysteresis. The proposed key provisioning is compatible with existing analog locking techniques and has a constant area overhead regardless of key size. This approach is tested with three analog/RF circuits to demonstrate its area scalability and effectiveness on security.

Multistage amplifiers are a reliable method of achieving high gain in systems where the voltage supply is low. The common practice is to prefer 3-stage amplifiers over 4-stage ones when a gain of2.This design achieved a unity-gain frequency (UGF) 1.18 MGz and a phase margin (PM) of 48° for all drivable load values. The proposed design, implemented in a standard CMOS 130-nm process, can drive a wide range of load capacitors without sacrificing any aspect of performance.

Similar to digital circuits, analog circuits are also susceptible to supply-chain attacks. There are several analog locking techniques proposed to combat these supply-chain attacks. However, there exists no elaborate evaluation procedure to estimate the resilience offered by these techniques. Evaluating analog defenses requires the usage of non-Boolean variables, such as bias current and gain. Hence, in this work, we evaluate the resilience of the analog-only locks and analog and mixed-signal (AMS) locks using satisfiability modulo theories (SMTs). We demonstrate our attack on five analog locking techniques and three AMS locking techniques. The attack is demonstrated on commonly used circuits, such as bandpass filter (BPF), low-noise amplifier (LNA), and low-dropout (LDO) voltage regulator. Attack results on analog-only locks show that the attacker, knowing the required bias current or voltage range, can determine the key. Likewise, knowing the protected input patterns (PIPs), the attacker can determine the key to unlock the AMS locks. We then extend our attack to break the existing analog camouflaging technique.

This article presents a fully differential (FD) low-voltage (LV) fourth-order Butterworth active-RC low-pass filter (LPF) with a maximum cutoff frequency (fo) of 160 MHz, foprogrammability, and adaptive power. The proposed filter targets communication systems requiring high and reconfigurable foat supply voltages (VDDs) of 0.6 V. The filter is implemented with an active-RC topology, a programmable fobetween four steps, 20/40/80/160 MHz, and a fofine-tuning option after fabrication via capacitor banks. A compact LV FD amplifier with feedforward gain-boosting implementation is used to meet the stringent filter's performance. The novel amplifier achieves an open loop gain of 66 dB and a maximum unity-gain frequency (UGF) of 759 MHz with VDD= 0.6 V and 5.27 mW of power dissipation. Using the proposed amplifier, the filter achieves the highest fo reported in the literature for LV active-RC implementations and 40% power reduction over similar high-foLV filters. The filter was fabricated in a CMOS 130-nm technology; it has a THD = 50.7 dB, signal-to-noise and distortion (SNDR) = 45.37 dB, P1dB= 4.26 dBm and 520-μV RMS integrated noise over the filter's bandwidth (BW), while consuming 23.8 mA from a 0.6-V supply for fo= 160 MHz.

Similar to digital circuits, analog circuits are also susceptible to supply-chain attacks, such as intellectual property (IP) piracy, counterfeiting, and overproduction. Hence, analog locking techniques have been proposed to combat supply-chain attacks. However, there exists no evaluation procedure to estimate the resilience offered by these defense techniques. Evaluating analog defense techniques requires the usage of non-Boolean variables, such as bias current, bias voltage, and gain. However, it cannot be handled by the Boolean satisfiability (SAT) attack. In this work, we propose an evaluation technique based on satisfiability modulo theories (SMT). We demonstrate our attack on four state-of-the-art analog locking techniques using commonly used circuits, such as bandpass filter (BPF), LC oscillator, quadrature oscillator, and class-D amplifiers. Our results show that the attacker, knowing the required bias current values, can determine the key in polynomial time. We also show that even if he/she has only partial information about the bias currents, the search space can be reduced from exponential to a polynomial number of keys. We then extend our attack to break existing analog camouflaging techniques.

Distributed on-chip voltage regulation is promising for addressing many IC power delivery challenges. However, complex interactions between active regulators and the surrounding parasitic passive RLC network cause stability concern. The recently developed hybrid stability technique provides a unique opportunity for coping with stability of distributed on-chip regulation and enabling efficient localized system design. However, the inherent conservativeness of the hybrid stability theorem (HST) leads to large pessimism in stability evaluation and hence causes overdesign. In this paper, the above challenge is addressed by extending the HST with an optimal frequency-dependent system partitioning technique which can significantly reduce the amount of pessimism in stability analysis. To put the proposed approach on a firm theoretical footing, we prove that the partitioning technique removes the conservativeness without altering the physical system and key theoretical properties of the partitioned blocks are maintained under certain constraints. Upon this, an efficient stability-ensuring power delivery design methodology using an automated design flow is developed to significantly improve power delivery performance. Within a large design space, the proposed approach ensures stability and improves system performance by up to 53%, measured by a figure of merit (FOM), when compared to the classical phase margin design approach, which provides no guarantee of stability. Furthermore, on average our approach boosts the FOM by 113% while consuming 11% less power compared to a reference hybrid stability approach.

This paper introduces a low-power wireless RF receiver for the wireless sensor network. The receiver has improved linearity with incorporated current-mode circuits and high-selectivity filtering. The receiver operates at the 900-MHz industrial, scientific, and medical band and is implemented in 130-nm CMOS technology. The receiver has a frequency multiplication mixer, which uses a 300-MHz clock from a local oscillator (LO). The LO is implemented using vertical delay cells to reduce power consumption. The receiver conversion gain is 40 dB and the receiver noise figure is 14 dB. The receiver's input third-order intercept point (IIP3) is -6 dBm and the total power consumption is 1.16 mW.

This work is based on the vision that the ultimate power integrity and efficiency may be best achieved via a heterogeneous chain of voltage processing starting from onboard switching voltage regulators (VRs), to on-chip switching VRs, and finally to networks of distributed on-chip linear VRs. As such, we propose a heterogeneous voltage regulation (HVR) architecture encompassing regulators with complimentary characteristics in response time, size, and efficiency. By exploring the rich heterogeneity and tunability in HVR, we develop systematic workload-aware power management policies to adapt heterogeneous VRs with respect to workload change at multiple temporal scales to significantly improve system power efficiency while providing a guarantee for power integrity. The proposed techniques are further supported by hardware-accelerated machine learning (ML) prediction of nonuniform spatial workload distributions for more accurate HVR adaptation at fine time granularity. Our evaluations based on the PARSEC benchmark suite show that the proposed adaptive three-stage HVR reduces the total system energy dissipation by up to 23.9% and 15.7% on average compared with the conventional static two-stage voltage regulation using off-chip and on-chip switching VRs. Compared with the three-stage static HVR, our runtime control reduces system energy by up to 17.9% and 12.2% on average. Furthermore, the proposed ML prediction offers up to 4.1% reduction of system energy.

Similar to digital circuits, analog and mixed-signal (AMS) circuits are also susceptible to supply-chain attacks such as piracy, overproduction, and Trojan insertion. However, unlike digital circuits, supply-chain security of AMS circuits is less explored. In this work, we propose to perform "logic locking" on digital section of the AMS circuits. The idea is to make the analog design intentionally suffer from the effects of process variations, which impede the operation of the circuit. Only on applying the correct key, the effect of process variations are mitigated, and the analog circuit performs as desired. We provide the theoretical guarantees of the security of the circuit, and along with simulation results for the band-pass filter, low-noise amplifier, and low-dropout regulator, we also show experimental results of our technique on a band-pass filter.

The Internet-of-Things (IoT) network is being vigorously pushed forward from many fronts in diverse research communities. Many problems are still there to be solved, and challenges are found among its many levels of abstraction. In this paper we give an overview of recent developments in circuit design for ultra-low power transceivers and energy harvesting management units for the IoT. The study shows how this research is contributing to enable new IoT applications, by reducing active power consumption and optimizing the extraction of energy from the ambient.

The continuing scaling of VLSI technology and design complexity has rendered robustness of analog circuits a significant concern. Parasitic effects may introduce unexpected marginal instability within multiple noise-sensitive loops and hence jeopardize circuit operation and processing precision. The Loop Finder algorithm has been recently proposed to allow detection of noise-sensitive return loops for circuits that are described using a linear time-invariant (LTI) system model. However, many practical circuits such as switched-capacitor filters and mixers present time-varying behaviors which are intrinsically coupled with noise propagation and introduce new noise generation mechanisms. For the first time, we take an in-depth look into the marginal instability of linear periodically time-varying (LPTV) analog circuits and further develop an algorithm for efficient identification of noise-sensitive loops, unifying the solution to noise sensitivity analysis for both LTI and LPTV circuits.

With a relatively small number of components, analog ICs are much more vulnerable to piracy, and especially reverse engineering, than many digital ICs. However, analog IC security has received much less research attention than digital ICs. We introduce a combinational locking technique using configurable current mirror for analog IC protection. The locking circuit is designed by applying Satisfiability Modulo Theories. With the locking system, only a single key value can make analog IC operate properly while the other key values result in significant performance degradation or malfunction. Moreover, circuit output is not monotone function with respect to key values and thus systematic attack is difficult to be effective. Experimental results demonstrate that this technique can largely thwart analog IC piracy with limited overhead.

This paper presents a voltage reference (VR) with a power supply rejection (PSR) better than 50 dB for frequencies of up to 60 MHz, and uses MOSFETs in strong inversion. Another innovation is a compact MOSFET low-pass filter, which was developed along with a feedback technique for a wide-bandwidth PSR not achieved in previous works. The proposed all-MOSFET VR was fabricated using a standard 0.18 μm CMOS process. It achieves a minimum temperature coefficient of 6.5 ppm/°C for temperatures from -30 °C to 110 °C. The line regulation is 0.076%/V for a step from 0.8 to 2.2 V supply voltage with 360 nW power consumption at room temperature and an area of 0.0143 mm2.

While distributed on-chip voltage regulation offers an appealing solution to power delivery, designing power delivery networks (PDNs) with distributed on-chip voltage regulators with guaranteed stability is challenging because of the complex interactions between active regulators and the bulky passive network. The recently developed hybrid stability theory provides an efficient stability checking and design approach, giving rise to highly desirable localized design of PDNs. However, the inherent conservativeness of the hybrid stability criteria can lead to pessimism in stability evaluation and hence large over-design. We address this challenge by proposing an optimal frequency-dependent system partitioning technique to significantly reduce the amount of pessimism in stability analysis. With theoretical rigor, we show how to partition a PDN system by employing optimal frequency-dependent impedance splitting between the passive network and voltage regulators while maintaining the desired theoretical properties of the partitioned system blocks upon which the hybrid stability principle is anchored. We demonstrate a new stability-ensuring PDN design approach with the proposed over-design reduction technique using an automated optimization flow which significantly boosts regulation performance and power efficiency.

This paper presents an on-chip, low drop-out (LDO) voltage regulator with improved power-supply rejection (PSR) able to drive large capacitive loads. The LDO compensation is achieved via a custom, wide bandwidth capacitance multiplier (c-multiplier) that emulates a nanofarad-range capacitance at the LDO output node. The LDO frequency response resembles that of externally compensated LDOs, leading to a wide PSR frequency range without using an off-chip capacitor. To drive large capacitive loads without stability concerns, the supply-line capacitance of the load circuit is incorporated to the design of the LDO compensation scheme. The power-stability-performance tradeoffs involved in the design are discussed in detail. The LDO and the c-multiplier are implemented in 0.18-μm CMOS technology and target applications with load currents in the 10-mA range. Experimental results show that the LDO achieves a PSR better than -39 dB up to 20 MHz at 1.2 V output voltage, while maintaining a 97.4% current efficiency.

Implementing a monolithic highly efficient ultralow photovoltaic (PV) power harvesting system is pivotal for smart nodes of Internet of things (IOT) networks. This paper proposes a fully integrated harvesting system in 0.18-μm CMOS technology. Utilizing a small commercial solar cell of 2.5 cm2, the proposed system can provide 0-29 μW of power, which is much higher than the commonly used passive radio-frequency identification devices in IOT application. The hill-climbing maximum power point tracking algorithm is developed in an energy-efficient manner to tune the input impedance of the system and guarantee adaptive maximum power transfer under wide illumination conditions. The detailed impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption as well as to achieve a higher efficiency than the traditional pulse-frequency modulation scheme. A supercapacitor is utilized for buffering, energy storing, and filtering purposes, which enables more functions of the IOT smart nodes such as active sensing and system-on-chip (SOC) signal processing. The output voltage ranges between 3.0 and 3.5 V for different device loads, such as sensors, SOC, or wireless transceivers. The measured results confirm that this PV harvesting system achieves both ultralow operation capability under 20 μW and a selfsustaining efficiency of 89%.

A lot of efforts have been done on software layer to propose the idea of Internet of Things (IoT). However, the functionality of IoT highly depends on the implementation of its end nodes. And there is little attention about realization of such IoT Smart Nodes. As mixed signal IC researchers, we analyze the urgent needs of IoT Smart Nodes and their implementation challenges. We focus this talk on the two of the most important practical issues: energy harvesting & regulating, and wireless transceiver.

This paper presents the design, analysis, and experimental verification of a self-calibrating current-reused 2.4-GHz direct-modulation transmitter for short-range wireless applications. The key contributions are the design/analysis of a stacked power amplifier (PA)/voltage-controlled oscillator (VCO) architecture, the nonlinear frequency-dependent analysis of a Gilbert-cell-based root-mean-square detector, and an on-chipLC-tank calibration circuit that needs no analog-to-digital convertor (ADC)/digital signal processor. The stacked architecture reduces the number of required regulators, utilizes supply headroom effectively, and allows for an “ADC-less” calibration loop that can dynamically tune the PA center frequency by sensing the transmitted signal. The very nature of direct-modulation architecture obviates additional high-purity signal generators, reducing complexity and allowing online calibration. The system was implemented in TSMC 0.18 μm CMOS, occupies 0.7 mm2(TX)+0.1 mm2(self-tuning), and was measured in a QFN48 package on an FR4 PCB. Automatically correcting PA/VCO tank misalignment in this case yielded >4 dB increase in output power. With the automatic tuning active, the transmitter delivers a measured output power >0 dBm to a 100-Ω differential load, and the system consumes 22.9 mA from a 1.8-V core-circuit supply.

A mathematical analysis of the effect of jitter and nonlinear inductance on THD+noise of class-D amplifiers is presented. In the analysis, it is assumed that jitter is not correlated between edges and has Gaussian distribution. It is shown that the nonlinear inductor in the output filter causes THD+noise to be frequency dependent. The relationship between jitter, nonlinear inductor and circuit parameters is formulated. The accuracy of the proposed mathematical approximation is verified by transistor level simulations.

A frequency synthesizer for a 2.4 GHz IEEE 802.15.4/Zigbee compliant transceiver is presented. The VCO has a 15.2% tuning range from 4580-5275 MHz with 135 MHz/V sensitivity. IQ generation for transceiver applications is performed through frequency division at the output of VCO. Frequency dividers employ hybrid circuit styles including CML and TSPC logic. The synthesizer is implemented in TSMC 0.18 μm CMOS technology. It occupies an area of 0.9 by 0.7 mm2only and consumes a total of 15mW from supply voltages of 3V, 1.8V and 1.3V.

There has been an increased interest in design of broadband (data rate >1MSPS) delta sigma ADCs with over-sampling ratios (OSR) as low as four. Most of these designs are switched capacitor based and use internal multi-bit DACs. With the widely used first order dynamic element matching, the SNDR of these converters is limited by the inherent capacitor matching. We propose a modified second order dynamic element matching technique to alleviate this problem for broadband ADCs, which target a SNDR greater than 100dB.

A CMOS RF RMS detector is introduced. It generates a DC proportional to the RMS voltage amplitude of an RF signal. Its high input impedance and small silicon area make it suitable for the built-in testing (BIT) of critical RF blocks of a transceiver such as a low noise amplifier (LNA) and power amplifier (PA) without affecting their performance and with minimum area overhead. The use of this structure in the fault detection and diagnosis of a wireless transceiver is described and illustrated with an example. The transistor-level implementation of the proposed circuit is discussed in detail. Post-layout simulation results using CMOS 0.35/spl mu/m technology show that this testing device is able to perform an RF to DC conversion at 2.4GHz in a dynamic range of 20dB using an area of only 0.0135mm/sup 2/ and presenting an equivalent input capacitance of 22.5fF.

A compact system for the on-chip transfer function characterization of an analog circuit is presented. It consists of a phase and amplitude detector and a signal generator. A general methodology for the use of this structure in the functional verification of a circuit under test (CUT) is provided. An integrated implementation of the proposed system in CMOS 0.35 /spl mu/m technology is described along with circuit-level design considerations. Experimental results of the application of this system in the characterization of a commercial programmable gain amplifier for frequencies up to 160 MHz are also presented.

In this paper, the design of variable gain ampli.er (VGA) for wireless receiver applications is presented. The VGA uses ac coupling (highpass filter) for dc offset rejection, while each VGA stage is designed to have constant output offset to overcome the slow response of the highpass filter. Due to the architecture chosen, The VGA has a fairly constant bandwidth in the entire gain range, and therefore it has constant settling time. It has been simulated and laid out using IBM SiGe BiCMOS 0.25Ām process. The VGA is OpAmp-R based and has gain range of -4 → 64dB with 2dB steps. It has about 35MHz bandwidth and consumes 1.5mA from 2.5V supply.

This paper presents a technique for programmable switched-capacitor (SC) filters based on periodical nonuniform individual sampling (PNIS) of each SC structure in the filter. It is shown how very wide range of programmability in all circuit parameters can be obtained, whereas the dynamic range degradation is kept minimum. Experimental results obtained from a 1.2 /spl mu/m CMOS second-order SC filter are given.

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The array median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on transconductance comparators to speed their time response, while the time delay is implemented using all-pass filters. Both circuits allow modular expansion for the implementation of large sized median filter array processors. In addition, a fast novel technique for parallel image processing is presented. It is shown that an image of 91/spl times/81 pixels is processed in less than 30 /spl mu/S using an array of high-speed analog processors. Experimental results of a test chip prototype in 2 /spl mu/m CMOS technology MOSIS process are presented.

A family of CMOS Operational Transconductance Amplifiers (OTA's) have been designed for very small G/sub M/'s (of the order of nA/V) in the moderate inversion region of operation using several design schemes such as current division, floating gate input stages and bulk driven techniques. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area and signal to noise ratio (SNR). The design has been sent for fabrication in a 1.2 /spl mu/m n-well CMOS process with a power supply of 2.7 V.

We proposed a novel technique for low voltage rail-to-rail constant-g/sub m/ input stages, which does not depend on the operation regions of the MOS transistors. An op amp was designed to demonstrate the new idea using MOSIS AMJ 1.2 /spl mu/m technology. A 2.5 MHz unity-gain bandwidth with 61/spl deg/ phase margin was achieved when driving 10 k/spl Omega/ and 10 pF load, with 240 /spl mu/A current consumption and a power supply of 3 V. The g/sub m/ variation of the input stage is within /spl plusmn/3% from rail-to-rail. By changing the bias current, the unity-gain bandwidth could be programmed from 90 kHz to 3 MHz.

A practical approach for generating precise and slow analog ramps to be used for time-domain analog testing and for monotonicity and histogram test of ADCs is presented. The technique uses a discrete-time adaptive scheme to calibrate the ramp generator. Two implementations of the approach are proposed: one is entirely single-ended and the second uses a pseudo-differential-based offset cancellation scheme. The first implementation has been implemented in 2 mm technology and experimental results are in agreement with simulations yielding a slope error of 1.5% and distortion of 0.2%.

Being able to fully test a circuit is an important issue for quality manufacturing. Unlike fault analysis for digital circuits, analog fault analysis has been comparatively slow to evolve. The purpose of this paper is to study the feasibility of the time domain response analysis as a test method for analog circuits. The approach was to first study the fault coverage obtained by testing the main parameters of the new NGCC amplifier, which shows the feasibility of built-in self test in time-domain. A circuit macromodel to implement a time-domain built-in self-test circuit was then proposed.

A practical system approach for time-multiplexing cellular neural network (CNN) implementations suitable for processing large and complex images using small CNN arrays is presented. For real size applications, due to hardware limitations, it is impossible to have a one-on-one mapping between the CNN hardware cells and all the pixels in the image involved. This paper presents a practical solution by processing the input image, block by block, with the number of pixels in a block being the same as the number of CNN cells in the array. Furthermore, unlike other implementations in which the output is observed at the hard-limiting block, the very large scale integrated (VLSI) architecture hereby described monitors the outputs from the state node. While previous implementations are mostly suitable for black and white applications because of the thresholded outputs, our approach is especially suitable for applications in color (gray) image processing due to the analog nature of the state node. Experimental complementary metal-oxide-semiconductor (CMOS) chip results in good agreement with theoretical results are presented.

Cork is a natural material produced in the Mediterranean countries. Cork stoppers are used to seal wine bottles, Cork stopper quality classification is a practical pattern classification problem. The cork stoppers are grouped into eight classes according to the degree of defects on the cork surface. These defects appear in the form of random-shaped holes, cracks, and others. As a result, the classification cork stopper is not a simple object recognition problem. This is because the pattern features are not specifically defined to a particular shape or size. Thus, a complex classification form is involved, Furthermore, there is a need to build a standard quality control system in order to reduce the classification problems in the cork stopper industry. The solution requires factory automation meeting low time and reduced cost requirements. This paper describes a cork stopper quality classification system using morphological filtering and contour extraction and following (CEF) as the feature extraction method, and a fuzzy-neural network as a classifier. This approach will be used on a daily basis. A new adaptive image thresholding method using iterative and localized scheme is also proposed, A fully functioning prototype of the system has been built and successfully tested. The test results showed a 6.7% rejection ratio, It is compared with the 40% counterpart provided by traditional systems. The human experts in the cork stopper industry rated this proposed classification approach as excellent.

Most class AB push-pull output buffers have been developed for supply voltages /spl ges/3.0 V. Recently developed class AB buffers, which operate at a voltage supply lower than 3.0 V, use sophisticated feedback circuits to control the quiescent current. In this paper, a simple class AB buffer is proposed. It can be used at 1.5 V power supply and has the capability to drive small resistive loads (<100 /spl Omega/). The circuit has been fabricated using a 1.2 /spl mu/ digital CMOS process. Experimental results demonstrate that the proposed circuit provides good control over the quiescent current. The standard deviation of the quiescent current is 17%. Combined with a floating gate input stage, a rail-to-rail input/output op amp has been fabricated and tested.

An integrated system for image processing is proposed. The main elements of the system consist of a cellular neural network (CNN) software simulator, multiplexing hardware, and an interface between a PC and the hardware and software.

A nonlinear parameterizable macromodel for CMOS Operational Transconductance Amplifiers (OTAs) is presented. The macromodel captures the DC, AC and large signal features of the transistor level original circuit, thus modeling accurately its time domain and nonlinear performance. The main contribution of this work is to account for the bias-dependent transconductance nonlinearities in the circuit, by curve-fitting the desired output characteristics with n-dimensional polynomials. The model can also account for the nonlinear dependence of the circuit's characteristics on several design parameters. The applicability of the model is demonstrated by modeling the response of an OTA-C filter.

The main difficulties in neural network (NN) hardware implementations are the massive connections and problem oriented topology. The authors propose an efficient general purpose discrete-time multiplexing neuron array (MNA) to deal with these problems. A versatile precise multiplier is presented. The proposed MNA can configurate various neural topologies and the size of networks can be easily augmented. The implementations of Multi-Layer Perceptron (MLP), Fully-Connected Recurrent (FCR) and Bidirectional Associated Memory (BAM) are considered as applications of the MNA. The MNA can be applied to any type of discrete-time circuit implementation. The basic building blocks are implemented with multipliers and switched-capacitor integrators. Experimental IC building blocks results are in good agreement with theoretical results.

A simple CMOS current-mode filter is presented. Its basic building block is a transconductor. It is comprised of a MOS transistor driver operating in the triode region cascoded with a MOS transistor current source at the output. This circuit can be employed in high-frequency continuous-time current-mode filters using a /spl plusmn/1 V power supply while dissipating less than 1 mW of power. To illustrate the methodology a second-order fully-differential bandpass filter with programmable f/sub 0/ and Q tuning is demonstrated. This filter dissipates less than 0.5 mW/pole with a /spl plusmn/1 V power supply and occupies an area of 0.6 mm/sup 2/ using a MOSIS Orbit 2 /spl mu/m CMOS technology.>

Two approaches for current-mode filters derived from canonical control structures are discussed. One of the approaches uses only lossy integrators. Both use transconductance multipliers to implement programmable transfer function coefficients. Experimental results are presented that verify the biquadratic structures.>

Presents a methodology for fault diagnosis of analog circuits based on the observation of power supply currents. In the proposed technique, fault signature dictionaries are generated from the currents in the power supply bus. To obtain signatures rich in information for efficient diagnosis, the transistors in the circuit are forced to operate in all regions of operation by using a ramp signal at the supply instead of the conventional constant dc signal. The signatures are then clustered into different groups using a Kohonen neural network classifier. This technique has the potential to detect and diagnose single and multiple shorts as well as open circuits. The theoretical and experimental results of the proposed technique are verified using a CMOS Operational Transconductance Amplifier (OTA) circuit.>

The transconductance-mode (T-mode) approach is extended to implement analog continuous-time neural network hardware systems to include on-chip Hebbian learning and on-chip analog weight storage capability. The demonstration vehicle used is a 5+5-neuron bidirectional associative memory (BAM) prototype fabricated in a standard 2-mum double-metal double-polysilicon CMOS process. Mismatches and nonidealities in learning neural hardware are not supposed to be critical if on-chip learning is available, because they will be implicitly compensated. However, mismatches in the learning circuits themselves cannot always be compensated. This mismatch is specially important if the learning circuits use transistors operating in weak inversion. The authors estimate the expected mismatch between learning circuits in the BAM network prototype and evaluate its effect on the learning performance, using theoretical computations and Monte Carlo HSPICE simulations. These theoretical predictions are verified using experimentally measured results on the test vehicle prototype.

A charge-based programmable Hamming neural network circuit is proposed. It utilizes capacitive comparators as processing elements in the feedforward layer, and a multiport charge-sensing amplifier as the MAXNET (or winner-take-all (WTA)) circuit. The CMOS prototype chip contains 10*10 fully interconnected processing elements with the capability of encoding 10 exemplar patterns. The whole circuit occupies a silicon area of 0.414 mm/sup 2/ fabricated in a 2- mu m CMOS technology. The low-silicon area and low-power dissipation are the fundamental properties of the proposed implementation. The experimental results from a prototype chip show robust retrieval and excellent classification properties as theoretically predicted. A modularity methodology and how to extend the prototype chip to VLSI system level integration are examined.>

A modular design approach for the CMOS implementation of a Hamming network is proposed. The Hamming network is an optimum minimum error classifier for binary patterns and is very suitable for a VLSI implementation due to its primarily feedforward structure. First, a modular chip that contains an array of NxM exclusive-NOR transconductors computes the matching scores between M encoded exemplar patterns (with N elements per exemplar) and an unknown input pattern. Then, a winner-take-all (WTA) circuit selects the exemplar pattern that most resembles the input pattern. By interconnecting multiple modular chips, the number and size of the patterns that can be stored in the network can be easily expanded. Measured experimental results are given to illustrate the performance and limitations of the hardware implementations of the Hamming network.

An area optimized computer-aided cascade switched-capacitor (SC) filter design program called AROMA is presented. The program contains several user-selectable filter approximation techniques. AROMA permits the user to make tradeoffs between several design parameters such as passive sensitivity, op-amp output voltage swings, clock frequency, and the total capacitance of the filter. The program has default values of the tradeoffs, however, each block in the cascade filter can be modified by the user to meet specific requirements. AROMA incorporates recent results of practical interest to the SC filter designer. The flexible structure of the program allows for easy addition of new results, i.e., refined efficient building blocks, additional filter approximations, etc. It can be used by the novice as well as by experienced designers. Furthermore, the program is user-oriented. It can start, in its simplest mode, with a set of frequency specifications. The output gives a circuit description file that can be layed out by an analog circuit layout generator program. Examples illustrating the practicalness of AROMA are given.