Article Share on Solving large scale assignment problems in high-level synthesis by approximative quadratic programming Authors: Florin Balasa University of Illinois at Chicago, Dept. EECS, Chicago, IL University of Illinois at Chicago, Dept. EECS, Chicago, ILView Profile , Werner Geurts Target Compiler Technologies, Leuven, B-3001, Belgium Target Compiler Technologies, Leuven, B-3001, BelgiumView Profile , Francky Catthoor Interuniv. Microelectronics Center, Katholieke Universiteit Leuven Interuniv. Microelectronics Center, Katholieke Universiteit LeuvenView Profile , Hugo De Man Interuniv. Microelectronics Center, Katholieke Universiteit Leuven Interuniv. Microelectronics Center, Katholieke Universiteit LeuvenView Profile Authors Info & Claims GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSIMarch 2001 Pages 19–24https://doi.org/10.1145/368122.368149Online:01 March 2001Publication History 1citation163DownloadsMetricsTotal Citations1Total Downloads163Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Embedded processors in electronic systems typically are tuned to a few applications. Development of processor-specific compilers is prohibitively expensive and, as a result, such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a processor model that captures the connectivity, the parallelism, and all architectural peculiarities of an embedded processor. We also implemented a retargetable and optimizing compiler working on this model. We present the graph-based processor model, and formally define the code generation task as binding the intermediate representation of an application to this model. We also present a new method for code selection, based on this processor model, that is capable of handling directed acyclic graphs instead of trees.

The increasing use of embedded software, often implemented on a core processor in a single-chip system, is a clear trend in the telecommunications, multimedia, and consumer electronics industries. A companion paper (Paulin et al., 1997) presents a survey of application and architecture trends for embedded systems in these growth markets. However, the lack of suitable design technology remains a significant obstacle in the development of such systems. One of the key requirements is more efficient software compilation technology. Especially in the case of fixed-point digital signal processor (DSP) cores, it is often cited that commercially available compilers are unable to take full advantage of the architectural features of the processor. Moreover, due to the shorter lifetimes and the architectural specialization of many processor cores, processor designers are often compelled to neglect the issue of compiler support. This situation has resulted in an increased research activity in the area of design tool support for embedded processors. This paper discusses design technology issues for embedded systems using processor cores, with a focus on software compilation tools. Architectural characteristics of contemporary processor cores are reviewed and tool requirements are formulated. This is followed by a comprehensive survey of both existing and new software compilation techniques that are considered important in the context of embedded processors.

In this paper, a novel technique for the synthesis of complex multifunctional units is presented. Given a set of functions, the goal is to minimize the area cost of a unit that can execute these functions. A set of primitive functional units is allocated and shared between operations which belong to different functions. In the presented approach, a bipartite matching-based technique is extended with a quadratic cost function which allows for a much more accurate modeling of interconnect cost compared to previous approaches. In the optimization process, functional unit type selection, instance allocation, and instance assignment are performed simultaneously. As an extension of the technique, a set of constraints which exclude solutions with false combinatorial cycles are also presented. The technique finds its main applicability in the synthesis of custom accelerator data paths in high throughput signal processing applications, as required in video, image processing, front end speech processing, and user-end telecom. In addition, it can be applied in the synthesis of the data path of domain-specific instruction set processors. Experiments show that highly optimized results can be obtained within acceptable CPU times.>

Many real-time signal processing applications are dominated by iterative loop constructs which exhibit a large amount of parallelism. In general, a realisation matched to the required rate of these applications exploits only a relatively small part of the parallelism available in the algorithm. This paper addresses the important problem of selecting the appropriate algorithmic-level decisions, in particular loop manipulations and the like, to arrive at an area-optimized specification for use in register-transfer level synthesis tools. One of the crucial cost factors in this optimisation is memory storage related. An effective model and methodology are proposed to derive an optimized architecture with fully matched throughput, while avoiding a full traversal of the large search space. The effectiveness of our approach is substantiated with several realistic test cases.>

In this paper, a novel technique for the synthesis of complex multi-functional units is presented. Given a set of functions or instructions, the goal is to minimize the area cost of a unit that can execute these functions. A common set of primitive functional units is allocated and shared between operations which belong to different functions. In the present approach, a bipartite matching based technique is extended with a quadratic cost function which allows for a much more accurate modeling of interconnect cost compared to previous approaches. In the optimization process, functional unit type selection, instance allocation and instance assignment are performed simultaneously. As an extension of the technique, a set of constraints which exclude solutions with false combinatorial cycles are also presented. Experiments show that highly optimized results can be obtained with acceptable CPU times.

The goal of this paper is to extend the synthesis of real