This brief introduces an adaptive continuous-time linear equalizer (CTLE) featuring a sub-sampled delay-locked loop (DLL) based clock recovery circuit. This circuit incorporates an inverse bang-bang phase detector (PD) that samples data at a one-sixteenth rate. A digitally tunable, inverter-based multiphase clock generator produces three clock phases for PD operation. The early and late signals from the PD output are used to estimate the eye opening of the incoming 4-level pulse amplitude modulation (PAM-4) data. Our adaptive algorithm utilizes the averaged early/late signals to digitally tune CTLE parameters, such as degeneration resistance and capacitance. The prototype chip, integrating both the CTLE and clock recovery circuit, is implemented in a 65 nm CMOS process. Post-layout simulations indicate a combined power consumption of 46.8 mW for the CTLE and clock recovery circuit at 40 Gb/s, achieving an energy efficiency of 1.17 pJ/b.

The article develops a novel motion model, called generalized multispeed Dubins motion model (GMDM), which extends the Dubins model by considering multiple speeds. While the Dubins model produces time-optimal paths under a constant-speed constraint, these paths could be suboptimal if this constraint is relaxed to include multiple speeds. This is because a constant speed results in a large minimum turning radius, thus producing paths with longer maneuvers and larger travel times. In contrast, multispeed relaxation allows for slower speed sharp turns, thus producing more direct paths with shorter maneuvers and smaller travel times. Furthermore, the inability of the Dubins model to reduce speed could result in fast maneuvers near obstacles, thus producing paths with high collision risks. In this regard, GMDM provides the motion planners the ability to jointly optimize time and risk by allowing the change of speed along the path. GMDM is built upon the six Dubins path types considering the change of speed on path segments. It is theoretically established that GMDM provides full reachability of the configuration space for any speed selections. Furthermore, it is shown that the Dubins model is a specific case of GMDM for constant speeds. The solutions of GMDM are analytical and suitable for real-time applications. The performance of GMDM in terms of solution quality (i.e., time/time-risk cost) and computation time is comparatively evaluated against the existing motion models in obstacle-free as well as obstacle-rich environments via extensive Monte Carlo simulations. The results show that in obstacle-free environments, GMDM produces near time-optimal paths with significantly lower travel times than the Dubins model while having similar computation times. In obstacle-rich environments, GMDM produces time-risk optimized paths with substantially lower collision risks.

We present a hybrid phase-detection based switching controller incorporating a look-up table (LUT) based finite state machine (FSM). This FSM can help in improving the settling response in fractional-N digital phase-locked loops (DPLLs). The settling time of the DPLL is further improved by using a grey counter-based coarse time-to-digital converter (TDC), which avoids metastability issues arising in binary counter-based TDC. A 2.7-5.5 GHz gear-shift mechanism based ring-oscillator fractional-N DPLL (FNDPLL) has been implemented in the CMOS 65-nm LL technology. The MATLAB and cadence simulation results of the FNDPLL show that the system with the reference clock ($F_{r\mathrm{e}f}$) of 100MHz can achieve a worst-case settling time of 3$\mu$s over an octave tuning range with 28 mW of power consumption.

In this work, we have proposed and experimentally demonstrated a true full-duplex input–output (TFD-IO) for high-speed high-density interfaces. The proposed TFD-IO can be used as an independent module that converts a unidirectional IO/interconnect to a fully bidirectional IO/interconnect, to ideally double the throughput of the high-speed interface. The TFD-IO uses a correlation-based technique to cancel the self-interference (SI) and echoes adaptively in the background. The signals transmitted from the near-end and the far-end can use independent baud-rates and signaling schemes in a TFD-IO. A proof-of-concept design of the TFD-IO module has been fabricated in a 65-nm CMOS technology, and demonstrated with bidirectional throughputs of up to 12.8 Gb/s.

The article presents a distributed algorithm, called Prediction-based Opportunistic Sensing for Resilient and Efficient Sensor Networks (POSE.R), where the sensor nodes utilize predictions of the targets' positions to probabilistically control their multi-modal operating states to track the targets. There are two desired features of the algorithm: energy efficiency and resilience. If the target is traveling through a high-node-density area, then an optimal sensor selection approach is employed that maximizes a joint cost function of remaining energy and geometric diversity around the target’s position. This provides energy efficiency and increases the network lifetime while preventing redundant nodes from tracking the target. However, if the target is traveling through a low-node-density area or in a coverage gap (e.g., formed by node failures or non-uniform node deployment), then a potential game is played amongst the surrounding nodes to optimally expand their sensing ranges via minimizing energy consumption and maximizing target coverage. This provides resilience, that is, the self-healing capability to track the target in the presence of low node densities and coverage gaps. The algorithm is comparatively evaluated against existing approaches through Monte Carlo simulations that demonstrate its superiority in terms of tracking performance, network-resilience, and network-lifetime.

The enhancement in the settling response of frequency synthesizers would open up prospects for new applications such as spread spectra and frequency hopping systems. Toward deriving a methodology for a fast settling response, we present a switched-loop digital phase locked loop (DPLL) incorporating an integral-derivative controller-based subsystem. The dominant features accelerating the settling response with low jitters in this DPLL are: 1) hybrid phase detection with a state machine using differential and double integration filtering effect and 2) a time-interleaved direct digital synthesizer (DDS)-based digital-to-time converter (DTC) with stable-edge sampling. A 5-GHz fractional-N DPLL (FNDPLL) has been implemented in CMOS 65-nm-LL technology with the proposed technique of loop-order switching. The measured results of the implemented FNDPLL highlight that the system is capable of fastest reported frequency settling to ±25-ppm error within 1.5 μs, using a reference clock frequency of 100 MHz. With one-time calibration, the downsampled output of DDS array-based phase interpolator achieves an integral nonlinearity (INL) of 0.25 ps, as a fractional divider in the loop.

In this paper, we propose a low power, high-resolution digitally controlled phase interpolator based clock and data recovery (CDR) architecture for high-speed serial links. This architecture incorporates a half-rate hybrid phase detector (HyPD) consisting of a linear phase detector with a 2-tap decision feedback equalizer (DFE), a 1-bit comparator, and an 8-bit digitally controlled phase interpolator. HyPD results in better power performance over the bang-bang phase detector. DFE used in HyPD combats the effect of inter-symbol-interference (ISI) and improves the sampling margins. The phase interpolator provides an unlimited phase capture with a resolution of 1.41° per LSB for varying phase of the input clock. The differential and integral nonlinearities of the DAC based phase interpolator are within ±0.28 LSB and ±0.3 LSB respectively, which lead to low jitter in the recovered clock. We have designed a 5 Gb/s CDR in a 0.18-μm standard CMOS technology. It draws 23.4 mW of power from a 1.8-V supply.

We propose an equi-probable line coding scheme for pulse amplitude modulation (PAM)-4. This encoding scheme can be used for improving the spectral efficiency of high speed serial links. Equi-probable PAM symbols also ensure atleast one zero-crossing transition in every encoded word, which is sufficient enough to recover the symbol clock from the received data. The equi-probable encoded words make design of the comparators at the receiver easy by aiding an automatic threshold tracking mechanism. This proposed encoding technique has a maximum contiguous symbol run length of 8, and ensures a DC balancing of encoded signals. The proposed 10S/12S encoding scheme has an overhead of 20%, as compared to the 25% overhead in the commonly used 8B/10B schemes.

A chiller plant consists of chiller, cooling tower, and pump subsystems. Two major configurations, primary-only and primary-secondary systems, are often used. Given the high energy costs of a plant, chiller plant operation optimization is important to save energy. For both configurations, chilled/condenser water supply temperatures are critical in improving chiller efficiency and should be considered as decision variables. However, nonlinearity of the problem is increased since chiller power consumption is a highly nonlinear function of these temperatures. Additionally, the problem is combinatorial considering the number of active units (e.g., chillers). In this paper, primary-only systems with identical units in each subsystem and primary-secondary systems with units of two sizes are studied, and both supply temperatures are optimized for energy savings. To obtain near-optimal solutions efficiently, a recent decomposition and coordination approach with little multiplier zigzagging and fast reduction of coupling constraint violations combining with sequential quadratic programming (SQP) is used. Penalties for the constraints that are difficult to be satisfied (e.g., mass balance constraints between fixed-speed pumps and variable-speed chillers) are added. After decomposition, complexity and nonlinearity of a subproblem are reduced drastically as compared with the original problem so that SQP is used. Numerical testing demonstrates that our approach is efficient in obtaining near-optimal solutions, and major energy savings are achieved as compared with benchmark strategies. The approach is scalable and can be used for chiller plant optimization and beyond.

This paper presents a distributed supervisory control algorithm that enables opportunistic sensing for energy-efficient target tracking in a sensor network. The algorithm called Prediction-based Opportunistic Sensing (POSE), is a distributed node-level energy management approach for minimizing energy usage. Distributed sensor nodes in the POSE network self-adapt to target trajectories by enabling high power consuming devices when they predict that a target is arriving in their coverage area, while enabling low power consuming devices when the target is absent. Each node has a Probabilistic Finite State Automaton which acts as a supervisor to dynamically control its various sensing and communication devices based on target's predicted position. The POSE algorithm is validated by extensive Monte Carlo simulations and compared with random scheduling schemes. The results show that the POSE algorithm provides significant energy savings while also improving track estimation via fusion-driven state initialization.

This paper presents an algorithm called ε*, for online coverage path planning of unknown environment. The algorithm is built upon the concept of an Exploratory Turing Machine (ETM), which acts as a supervisor to the autonomous vehicle to guide it with adaptive navigation commands. The ETM generates a coverage path online using Multiscale Adaptive Potential Surfaces (MAPS), which are hierarchically structured and dynamically updated based on sensor information. The ε*-algorithm is computationally efficient, guarantees complete coverage, and does not suffer from the local extrema problem. Its performance is validated by 1) high-fidelity simulations on Player/Stage and 2) actual experiments in a laboratory setting on autonomous vehicles.

Border surveillance requires regular patrolling to prevent intruders from crossing across, emphasizing the need for an automated network of sensing devices that is capable of detecting and estimating multiple moving targets. This paper proposes a fusion-driven decentralized sensor scheduling scheme that enables dynamic space-time clustering around multiple moving targets for energy-efficient track estimation. Each sensor node runs a Probabilistic Finite State Automata (PFSA) that controls the sensing and communication devices in an energy-efficient manner. This decentralized scheduling scheme is validated and compared with traditional scheduling schemes. The results show that the proposed scheme conserves energy while maintaining accurate track estimation.

Human activity recognition has become an increasingly important field of research with many practical applications related to health care and leisure activities. The accessibility of inexpensive portable sensors, such as accelerometers, allows for a widespread use of this technology for both commercial and personal activity recognition. This paper develops a novel feature extraction approach to human activity recognition through the development of the Lempel-Ziv-Welch Coded Probabilistic Finite State Automata (LZW-Coded PFSA) to classify activities such as walking, jumping, running, waist rotations, and shoulder rotations. The PFSA reveal the underlying architecture of a given activity and classify it without making any a priori assumptions by inferring patterns from the sensor measurements. LZW-Coded PFSA select the optimal variable length state from the time-series data and compress it into class-separable state transition matrices π. This algorithm is robust to subject biases and is shown to be effective with a correct classification rate of 95.63%.

This paper presents an inductorless full rate pseudo-random binary sequence generator (PRBSG). Data rate of the PRBSG can be enhanced by 23% using internal pre-emphasis. The technique uses D flip-flops (DFFs) as 1-tap decision feedback equalizers (DFE) to equalize the outputs of the previous DFFs. This makes every DFF a DFE circuit, which is also used as a delay element for the PRBSG. The proposed technique increases the data-rate of the PRBSG significantly with minor increase in area and power. A design methodology to find the feedback factor of pre-emphasis technique using least square estimation is also presented. Post layout simulation in standard 90 nm CMOS technology of the 27-1 PRBSG confirms operation of the circuit at a data-rate of 13 Gb/s with peak to peak jitter of 8 ps, while consuming 222 mW off a 1 V supply, without using inductors.

Even self-deployment is one of the best strategies to deploy mobile sensors when the region of interest is unknown and manual deployment is infeasible. A widely used distributed algorithm, Lloyd`s method, can achieve even self-deployment. It however suffers from two critical issues when being used in mobile sensor networks. First, it does not consider limited sensor communication range. Second, it does not optimize sensor movement distances, and hence can lead to excessive energy consumption, a primary concern in sensor networks. This paper first formulates a locational optimization problem that achieves even deployment while it takes account of energy consumption due to sensor movement, and then proposes two iterative algorithms. The first algorithm, named Lloyd- α, reduces the movement step sizes in Lloyd`s method. It saves traveling distance while maintaining the convergence property. However, it leads to a larger number of deployment steps. The second algorithm, named Distributed Energy-Efficient self-Deployment (DEED), reduces sensor traveling distances and requires a comparable number of deployment steps as that in Lloyd`s method. This paper further proposes an intuitive method to deal with limited sensor communication range that is applicable to all three methods. Extensive simulation using NS-2 demonstrates that DEED leads to up to 54 percent less traveling distance and 46 percent less energy consumption than Lloyd`s method.

Testing of high-speed Digital-to-Analog Converters (DACs) is a challenging task, as it requires large number of high-speed synchronized input signals with specific test patterns. To overcome this problem, we propose use of PRBS signals with an “Alternate-Bit-Tapping” technique and eye-diagram measurement as a solution to efficiently generate the test-vectors and test the DACs. This approach covers all levels and transitions necessary for testing the dynamic behavior of the DAC completely, in minimum possible time. Circuit level simulations are used to verify its usefulness in testing a 4-bit 20-GS/s current-steering DAC.

This paper presents a statistical-mechanics-inspired procedure for optimization of the sensor field configuration to detect mobile targets. The key idea is to capture the low-dimensional behavior of the sensor field configurations across the Pareto front in a multiobjective scenario for optimal sensor deployment, where the nondominated points are concentrated within a small region of the large-dimensional decision space. The sensor distribution is constructed using location-dependent energy-like functions and intensive temperature-like parameters in the sense of statistical mechanics. This low-dimensional representation is shown to permit rapid optimization of the sensor field distribution on a high-fidelity simulation test bed of distributed sensor networks.