The quadrature phase clocks are important elements in digital programmable transceivers in communication system applications. However, current solutions in quadrature clock generators for broad frequency ranges need more phase accuracy, and they suffer from substandard phase noise performance and excessive power consumption. To address these challenges, this paper proposes an inverter-based quadrature-phase clock (I-QPC) generator. The I-QPC generator utilizes inverters as delay elements to achieve the desired phase without using poly-phase type-1 filters because inverters are simpler to design and optimize for different phase delays. The system implements a phase-averaging mechanism using the delayed and interpolated signals, leading to quadrature-phase signals. The proposed technique has been validated in 28nm standard CMOS technology after post-layout parasitic extraction. The I-QPC generator operates over the broad frequency range (1GHz to 6GHz) and occupies an active area of 0.0005mm2. The post-layout simulation results show that the phase error is ±0.29°while operating at 6GHz. The phase noise is -131.7dBc/Hz at an offset of 1MHz with a power consumption of 2.9mW. The I-QPC generator’s figure of merit (FoM) is 217.3dBc/Hz at 1MHz offset frequency, which is better than state-of-the-art architectures. The performance of the I-QPC generator was further evaluated in hardware by implementing the circuit on a breadboard using the SN74HC04N inverter IC, and it demonstrated the successful generation of the quadrature signals at 1MHz frequency.

This paper presents a fixed transconductance circuit based on the impedance matching. The proposed technique does not depend on the square law model of the transistors and tracks the resistor for all operating regions of the transistor. Unlike its predecessors, the transconductance of the transistor tracks for a wide range of external resistors. Such techniques find applications in analog and mixed-signal circuits like data converters, voltage- controlled oscillators, amplifiers, etc. The proposed circuit is implemented in the TSMC 65nm LP process, and it occupies an area of 55μm x 24μm. The transconductance varies about 0.8% over a nominal value of 125μS across process corners and temperature. Monte Carlo simulation results show a standard deviation of 4.64 μS over a mean of 125.8 μS.

Traditional Banba bandgap is very popular in deep sub-micron CMOS technologies because of its sub 1V output nature. But unfortunately, it won’t provide PTAT nature current and has several operating points, unlike two in the voltage mode BGR. This work analyzes the Banba circuit in a detailed way so that it’s easy to demonstrate multiple stable operating and lists some of its other shortfalls. This paper presents a novel sub-1V bandgap architecture, which can provide PTAT current and sub-1V output without having multiple operating points. A modified self-bias opamp has been proposed to minimize the systematic offset and its temperature drift. A prototype was developed in 28nm TSMC CMOS technology and post-layout simulation results were performed. Proposed BGR targeted at 500mV works from 1V supply without having any degradation in the performance while keeping the integrated noise of $18.2 \mu \text{V}$ and accuracy of $17.1ppm/^{\mathbf{0}}C$, while the traditional Banba was resulting $23.4ppm/^{\mathbf{0}}C$. Further, the circuit consumes ($29.8 \mu \text{W}$) of power and occupies $71*(39 \mu \text{m})^{\mathbf{2}}$silicon area.

In this paper, a curvature-compensated bandgap reference circuit is presented which generates 0.538V from 0.85V supply voltage. The PTAT voltage generated in the bandgap core is added to the partial CTAT voltage to generate the sub-bandgap reference, reducing the CTAT current mirror mismatch. Furthermore, this architecture eases the opamp's requirements on offset and flicker noise significantly and doesn't require sophisticated techniques, such as chopping. A novel curvature compensation scheme is proposed and validated across PVT simulations and achieves 12 ppm/°C with a single point trim. The proposed bandgap consumes a power of 15 μW and occupies an area of 7315 μm2in TSMC 28nm.