Demo Data from EDBT 2026 / reviewers in the wild / expert
Ruediger Willenberg
dblp:18/9033 · also Rüdiger Willenberg
· DBLP profile ↗
5ranked-venue papers
5as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 5 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 44% Reconfigurable computing and FPGAs · 28% Distributed systems · 28% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA-based heterogeneous computing |
0.2 | 1 | 2013 | A remote memory access infrastructure for global address space programming models in FPGAs · FPGA 2013 |
Parallel and multicore computing › parallel programming models › distributed memory programming models
global address space programming |
0.2 | 1 | 2013 | A remote memory access infrastructure for global address space programming models in FPGAs · FPGA 2013 |
Distributed systems › distributed communication
remote memory access |
0.2 | 1 | 2013 | A remote memory access infrastructure for global address space programming models in FPGAs · FPGA 2013 |
Parallel and multicore computing
parallel programming models |
0.0 | 1 | 2013 | A remote memory access infrastructure for global address space programming models in FPGAs · FPGA 2013 |
Parallel and multicore computing › parallel programming models › distributed memory programming models
partitioned global address space |
0.0 | 1 | 2013 | A remote memory access infrastructure for global address space programming models in FPGAs · FPGA 2013 |
Methods — techniques the papers use, named apart from their topics
active messages · 0.2GASNet · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | A remote memory access infrastructure for global address space programming models in FPGAsabstractWe are proposing a shared-memory communication infrastructure that provides a common parallel programming interface for FPGA and CPU components in a heterogeneous system. Our intent is to ease the integration of reconfigurable hardware into parallel programming models like Partitioned Global Address Space (PGAS). For this purpose, we introduce a remote memory access component based on Active Messages that implements the core API of the Berkeley GASNet communication library, and a simple controller that manages communication and synchronization for custom FPGA cores. We demonstrate how these components deliver a simple and easily configurable communication mechanism between distributed memories in a multi-FPGA system with processors as well as custom hardware nodes. Ruediger Willenberg, Paul Chow |
FPGA | 1 |
| 2013 | Simulation-based HW/SW co-debugging for field-programmable systems-on-chipabstractWe are presenting SimXMD (Simulation-based eXperimental Microprocessor Debugger), a tool that allows developers to debug microcontroller code and custom hardware simultaneously. SimXMD connects a GNU debugger instance to a full-system simulation of an embedded FPGA system. This enables free-roaming investigation of hardware-software interactions inside the system, including reverting back to an earlier point in simulation time. A custom memory logging mechanism enables access to variables in on-chip, off-chip and cached memory. SimXMD is open source, and its modular architecture facilitates extension to other embedded processors as well as different simulators and debuggers. Ruediger Willenberg, Paul Chow |
FPL | 1 |
| 2013 | SimXMD: Simulation-based HW/SW co-debuggingabstractThe unique promise of embedded systems in FPGAs is that designers can develop and modify their own peripheral hardware with a high degree of flexibility. However, the task of verifying the hardware commonly involves writing software to interact with it. This software itself is prone to design errors. To debug a system with two untested interacting components, it is preferable if their interaction can be precisely traced. We are presenting SimXMD (Simulation-based eXperimental Microprocessor Debugger), a tool that allows developers to debug microcontroller code and custom hardware simultaneously. The concept of debugging hardware and software together is not a new one. However, we take two established tools already used by the respective developers and connect them in a transparent way. SimXMD connects a GNU debugger (GDB) instance to a full-system simulation of an embedded FPGA system in ModelSim. This enables free-roaming investigation of hardware-software interactions inside the system, including reverting back to an earlier moment in simulation time. Software can be debugged in the same way that it would be commonly done with a real implementation on an FPGA board. Ruediger Willenberg, Paul Chow |
FPL | 1 |
| 2012 | SimXMD: Integrated debugging of C code and hardware componentsabstractIn our demonstration, we present SimXMD, a tool that enables developers to debug microcontroller code and custom hardware simultaneously. SimXMD (Simulated eXperimental Microprocessor Debugger). SimXMD connects a GNU Debugger instance to a ModelSim instance simulating an embedded FPGA system with a Xilinx Microblaze processor. We will demonstrate debugging a multiprocessor FPGA system where the processor cores are connected through custom-designed network hardware. SimXMD is Open Source, and its modular architecture facilitates extending it to other embedded processors as well as different simulators or debuggers. Ruediger Willenberg, Paul Chow |
FPT | 1 |
| 2010 | Generation of Deterministic MCU/FPGA Hybrid Systems from UML ActivitiesabstractIn this paper, we extend a model-driven design process for embedded systems to FPGA target platforms. We introduce a VHDL code framework that implements buffered data flow structures and encapsulates hand-written computation kernels. We demonstrate how a toolchain uses the framework to generate system code from behavioral models called activity diagrams. Further, we introduce an interface solution that allows the designer to model and generate hybrid systems of microcontrollers and FPGAs together. Finally, we present a case study for cross-platform system implementation. Ruediger Willenberg, Zamira Daw, Christian Englert, Marcus Vetter |
FPL | 1 |