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Alex D. Brant

dblp:18/9240 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 39% Memory systems · 30% Processor architecture and microarchitecture · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › on-chip memory
scratchpad memory
0.112011
VEGAS: soft vector processor with scratchpad memory · FPGA 2011
Reconfigurable computing and FPGAs › reconfigurable architecture › reconfigurable processor
soft vector processor
0.112011
VEGAS: soft vector processor with scratchpad memory · FPGA 2011
Processor architecture and microarchitecture
vector processor
0.112011
VEGAS: soft vector processor with scratchpad memory · FPGA 2011
Reconfigurable computing and FPGAs › FPGA-based processor implementation
soft-core processor
0.012011
VEGAS: soft vector processor with scratchpad memory · FPGA 2011

Methods — techniques the papers use, named apart from their topics

C macro API · 0.1
YearPublicationVenuePosition
2011 VEGAS: soft vector processor with scratchpad memory
abstract
This paper presents VEGAS, a new soft vector architecture, in which the vector processor reads and writes directly to a scratchpad memory instead of a vector register file. The scratchpad memory is a more efficient storage medium than a vector register file, allowing up to 9x more data elements to fit into on-chip memory. In addition, the use of fracturable ALUs in VEGAS allow efficient processing of bytes, halfwords and words in the same processor instance, providing up to 4x the operations compared to existing fixed-width soft vector ALUs. Benchmarks show the new VEGAS architecture is 10x to 208x faster than Nios II and has 1.7x to 3.1x better area-delay product than previous vector work, achieving much higher throughput per unit area. To put this performance in perspective, VEGAS is faster than a leading-edge Intel processor at integer matrix multiply. To ease programming effort and provide full debug support, VEGAS uses a C macro API that outputs vector instructions as standard NIOS II/f custom instructions.
Christopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy Lemieux
FPGA3