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Hoshik Kim

dblp:18/943 · DBLP profile ↗
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2ranked-venue papers
0as first author
2since 2021 · last 2026
0000-0002-4017-8124ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 58% Cloud and datacenter computing · 17% Parallel and multicore computing · 13%

Topics — the 8 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory disaggregation
CXL memory
1.012026
Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack · IEEE Trans. Computers 2026
Memory systems › memory management
heterogeneous memory management
1.012026
Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack · IEEE Trans. Computers 2026
Memory systems › processing-in-memory
near-memory processing
1.012026
Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack · IEEE Trans. Computers 2026
Memory systems
processing-in-memory
1.012026
Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack · IEEE Trans. Computers 2026
Cloud and datacenter computing › resource disaggregation
CXL memory sharing
0.912025
cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications · SC 2025
Parallel and multicore computing › parallel computing › parallel communication
inter-node communication
0.912025
cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications · SC 2025
Hardware accelerators and domain-specific architectures
nearest neighbor search
0.312026
Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack · IEEE Trans. Computers 2026
Storage systems › data management › storage for machine learning
vector database
0.312026
Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack · IEEE Trans. Computers 2026

Methods — techniques the papers use, named apart from their topics

dax · 0.9cache coherence · 0.9atomic operations · 0.9CXL memory sharing · 0.9
YearPublicationVenuePosition
2026 Toward Deployable CXL-PNM: The CMM-Ax Prototype and Software Stack
abstract
Processing-Near-Memory (PNM) over Compute Express Link (CXL) has strong architectural appeal. However, most existing CXL-attached PNM prototypes remain inflexible or simulation-based and lack integration with full software stacks, which limits their practical deployment. This work introduces CMM-Ax, a deployable hybrid CXL-PNM system that combines streaming near-memory pipelines with device-side programmability and integrates tightly with the Heterogeneous Memory Software Development Kit (HMSDK). Through HMSDK, CMM-Ax exposes CXL-attached memory via standard Linux allocation paths (e.g., malloc and mmap). This allows existing vector databases and search engines to adopt heterogeneous memory with minimal application-level changes, such as selecting the CMM-Ax FAISS backend. CMM-Ax further provides a comprehensive software stack—FAISS integration, a domain-specific compiler for user-defined operators, and a Kubernetes device plugin supporting multi-tenant slicing—capabilities not demonstrated in prior CXL-PNM. Using an FPGA-based CXL Type-3 prototype, CMM-Ax achieves 4.54× higher throughput and 5.56× lower energy per query than a CXL memory-only baseline on the exact k-nearest neighbor (kNN) search. For approximate nearest neighbor (ANN) inverted-file (IVF) workloads, CMM-Ax sustains bandwidth-proportional efficiency at small batches (batch=1: 37% vs. 12% CPU, 7% GPU). In Kubernetes deployments, CMM-Ax–equipped servers can replace a significantly larger CPU-only cluster at equivalent memory capacity and throughput, reducing node count and system energy.
Kwangsik Shin, KangKyu Park, Joonseop Sim, Thomas Won Ha Choi, Youngpyo Joo, Hoshik Kim
IEEE Trans. Computers6
2025 cMPI: Using CXL Memory Sharing for MPI One-Sided and Two-Sided Inter-Node Communications
abstract
Message Passing Interface (MPI) is a foundational programming model for high-performance computing. MPI libraries traditionally employ network interconnects (e.g., Ethernet and InfiniBand) and network protocols (e.g., TCP and RoCE) with complex software stacks for cross-node communication.This paper presents cMPI, the first work to optimize MPI point-to-point communication (both one-sided and two-sided) using CXL memory sharing on a real CXL platform, transforming cross-node communication into memory transactions and data copies within CXL memory, bypassing traditional network protocols. We analyze performance across various interconnects and find that CXL memory sharing achieves 7.2 × -8.1 × lower latency than TCP-based interconnects deployed in small- and medium-scale clusters. We address challenges of CXL memory sharing for MPI communication, including data object management over the dax representation [50], cache coherence, and atomic operations. Overall, cMPI outperforms TCP over standard Ethernet NIC and high-end SmartNIC by up to 49 × and 72 × in latency and bandwidth, respectively, for small messages.
Xi Wang 0027, Bin Ma 0025, Jongryool Kim, Byungil Koh, Hoshik Kim, Dong Li 0001
SC5