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Satoshi Iida

dblp:18/9928 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Graphics, computer vision, multimedia, augmented reality and games · 1Human-computer interaction and ubiquitous computing · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 40% Electronic design automation · 40% Hardware reliability and fault tolerance · 20%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design › logic gate design
CMOS gate		 0.112011
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates · DAC 2011
Integrated circuit design
digital circuit design		 0.112011
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates · DAC 2011
Electronic design automation › timing analysis
statistical timing analysis		 0.112011
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates · DAC 2011
Electronic design automation
timing analysis		 0.112011
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates · DAC 2011
Hardware reliability and fault tolerance › process variation
within-die variation		 0.112011
A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates · DAC 2011

Methods — techniques the papers use, named apart from their topics

monte carlo simulation · 0.1
YearPublicationVenuePosition
2013 A Face-Like Structure Detection on Planet and Satellite Surfaces Using Image Processing
Kazutaka Kurihara, Masakazu Takasu, Kazuhiro Sasao, Hal Seki, Takayuki Narabu, Mitsuo Yamamoto, Satoshi Iida, Hiroyuki Yamamoto
 Advances in Computer Entertainment7
2011 A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates
abstract
In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process.
Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
 DAC2
2011 Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS
Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
 ISLPED2