EDBT 2026 Demo / reviewers in the wild / expert
Jae Young Jang
dblp:180/0096
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2016
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Energy-efficient computing · 44% GPUs and heterogeneous computing · 44% Parallel and multicore computing · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing
power management |
0.2 | 1 | 2016 | Workload-Aware Optimal Power Allocation on Single-Chip Heterogeneous Processors · IEEE Trans. Parallel Distributed Syst. 2016 |
GPUs and heterogeneous computing › heterogeneous architecture
single-chip heterogeneous processor |
0.2 | 1 | 2016 | Workload-Aware Optimal Power Allocation on Single-Chip Heterogeneous Processors · IEEE Trans. Parallel Distributed Syst. 2016 |
Parallel and multicore computing › parallel scheduling
runtime scheduling |
0.1 | 1 | 2016 | Workload-Aware Optimal Power Allocation on Single-Chip Heterogeneous Processors · IEEE Trans. Parallel Distributed Syst. 2016 |
Methods — techniques the papers use, named apart from their topics
run-time algorithm · 0.2optimization · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | Workload-Aware Optimal Power Allocation on Single-Chip Heterogeneous ProcessorsabstractAs technology scales below 32 nm, manufacturers began to integrate both CPU and GPU cores in a single chip, i.e., single-chip heterogeneous processor (SCHP), to improve the throughput of emerging applications. In SCHPs, the CPU and the GPU share the total chip power budget while satisfying their own power constraints, respectively. Consequently, to maximize the overall throughput and/or power efficiency, both power budget and workload should be judiciously allocated to the CPU and the GPU. In this paper, we first demonstrate that optimal allocation of power budget and workload to the CPU and the GPU can provide 13 percent higher throughput than the optimal allocation of workload alone for a single-program workload scenario. Second, we also demonstrate that asymmetric power allocation considering per-program characteristics for a multi-programmed workload scenario can provide 9 percent higher throughput or 24 percent higher power efficiency than the even power allocation per program depending on the optimization objective. Last, we propose effective runtime algorithms that can determine near-optimal or optimal combinations of workload and power budget partitioning for both single- and multi-programmed workload scenarios; the runtime algorithms can achieve 96 and 99 percent of the maximum achievable throughput within 5-8 and 3-5 kernel invocations for single- and multi-programmed workload cases, respectively. Jae Young Jang, Hao Wang 0011, Euijin Kwon, Jae W. Lee, Nam Sung Kim |
IEEE Trans. Parallel Distributed Syst. | 1 |