In the interest of alleviating qubit coherence constraints and making quantum control circuits more efficient, this paper explores qubit control using superconducting Single-Flux Quantum (SFQ) digital circuits. By using SFQ pulse trains and SFQ switches, we represent qubit state transformations through their equivalent phase changes, where each SFQ pulse represents a phase change of certain degrees. We propose classical-based unitary quantum gates represented by SFQ pulses. We create a classical equivalent model for quantum gates based on an SFQ-based parametric pulse sequence equivalent to quantum Pauli gates. To generate pulse sequences of configurable parameters, we implement a versatile multi-frequency pulse generator that seamlessly integrates with the qubit-resonator cavity.

Triangle counting is a graph kernel that reveals information about the communities in real-world networks. Recently, circuits that employ time-domain as opposed to traditional binary computing have been developed to try and improve the energy efficiency and throughput of multiple graph processing problems. Here, we explore the tradeoffs of using race logic (RL), where inputs are encoded as timing delays, to count triangles in a graph through neighbor-set intersection. Using theoretical analysis, we investigate the scaling efficiency when using a circuit of fixed dimension to find the intersection between sets of different sizes. We investigate three different circuit array sizes: the dimension that minimizes latency, the dimension that is ideal for processing sets of the mean length, and the dimension 3 X 3. We evaluate the energy efficiency and throughput of the proposed circuit and find that our approach demonstrates the most improvement over current state-of-the-art (SOTA) with unimodal, right-skewed, and low range set-length distributions such as road networks.

We present an area-efficient, asynchronous, single-input, and multiple-output Rapid Single Flux Quantum (RSFQ) pulse round-robin distribution network. We adopt the structure of a two-output toggle flip flop (TFF) where incoming pulses are temporarily stored in a SQUID loop in the form of magnetic flux quanta and then directed to outputs in a round-robin fashion. To support additional toggle outputs, we design a new circuit based on TFFs to distribute pulses in a round-robin mechanism to more than two outputs. We also elaborate on our design methodology that can support a different number of outputs while minimizing the number of JJs and power consumption. We then demonstrate a three- and four-output round-robin distribution network constructed with only 14-JJs and 18-JJs with$14.85 ~\mu W$and 18.86-$\mu W$power dissipation, respectively. Our four-output design has 40%–70% fewer JJ compared to a similar-functioning four-output network composed of TFFs, DFFs, splitters, and mergers. Our design also consumes 38%–70% less power and has a 16%–64% reduced delay compared to the same four-output TFF network. Finally, we demonstrate the usability of our four-output design in the context of a periodic counting network and pulse generator.

This paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of$3.6~\mu W$and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.

Superconducting technology is a prime candidate for the future of computing. However, current superconducting prototypes are limited to small-scale examples due to stringent area constraints and complex architectures inspired from voltage-level encoding in CMOS; this is at odds with the ps-wide Single Quantum Flux (SFQ) pulses used in superconductors to carry information. In this work, we propose a wave-pipelined Unary SFQ (U-SFQ) architecture that leverages the advantages of two data representations: pulse-streams and Race Logic (RL). We introduce novel building blocks such as multipliers, adders, and memory cells, which leverage the natural properties of SFQ pulses to mitigate area constraints. We then design and simulate three popular hardware accelerators: i) a Processing Element (PE), typically used in spatial architectures; ii) A dot-product-unit (DPU), one of the most popular accelerators in artificial neural networks and digital signal processing (DSP); and iii) A Finite Impulse Response (FIR) filter, a popular and computationally demanding DSP accelerator. The proposed U-SFQ building blocks require up to 200× fewer JJs compared to their SFQ binary counterparts, exposing an area-delay trade-off. This work mitigates the stringent area constraints of superconducting technology.

Temporal encoding has been shown to be a natural fit for single flux quantum (SFQ) superconducting computing since SFQ already encodes information with the presence or absence of voltage pulses. However, past work in SFQ has focused on binary-encoded networks on chip (NoCs). In this paper, we propose superconducting rotary NoC (SRNoC), a NoC where both data and control paths operate in the temporal domain following the race logic (RL) convention. Therefore, SFQ chips with temporal compute or memory can use SRNoC to avoid converting between the temporal and binary domains that would result from using a binary-encoded NoC. Using RL also enables SRNoC to be area-efficient, mitigating SFQ technology's low device density. SRNoC treats pulses as independent packets and delivers them to outputs without changing their value, i.e. preserving the RL convention. SRNoC operates on a fixed, rotating connection schedule between inputs and outputs. In each connection window, multiple pulses (packets) can be transmitted sequentially. SRNoC provides 13.1x higher throughput per port per Josephson junction (JJ) compared to the best-performing of three demonstrated NoCs.

A design methodology using quasi-lumped elements for compact millimeter-wave on-chip bandpass filter (BPF) is presented in this work. To implement BPF using this approach, a novel inductor cell is presented first and then using this cell along with metal-insulator-metal (MIM) capacitors, two BPFs are designed. For the purpose of proof-of-concept, all three designs are implemented and fabricated in a standard 0.13-μm (Bi)-CMOS technology. The measurements show that the inductor cell generates a notch at 47 GHz with a chip size of 0.096 × 0.294 mm2without pads. Moreover, the 1st BPF has the center frequency at 27 GHz with an insertion loss of 2.5 dB and it has one transmission zero at 58 GHz with a peak attenuation of 23 dB. Unlike the 1st design, the 2nd design has two transmission zeros. The center frequency of this BPF is located at 29 GHz with a minimum insertion loss of 3.5 dB. Without the measurement pads, the chip sizes of the two BPFs are 0.076 × 0.296 mm2and 0.096 × 0.296 mm2, respectively.

This paper presents the design of a differential double-balanced Gilbert mixer in 0.13 um SiGe BiCMOS technology. A current-bleeding injection technique is adopted to increase the bias current at the driver stage without causing overvoltage headroom at the differential pair stage. This mechanism improves the performance in terms of conversion gain, linearity and noise figure. The proposed mixer achieves 10.7 dB conversion gain, 15 dB noise figure, -1.67 dBm 1-dB compression point, and 5 dBm IIP3. The designed double balanced Gilbert mixer with current bleeding is part of an integrated RF front-end for full duplex radio applications in the 2.4 GHz band and occupies an area of 0.1002 × 0.0748 mm2 excluding the pads.

Design of high-performance continuous- time filter (CTF) for analogue signal processing is presented in this paper. To demonstrate of using a novel voltage-mode multiple-loop feedback (MLF) approach for CTF design, a 5th-order elliptic lowpass filter (LPF) is implemented in a standard 0.18-μm CMOS technology. The LPF is based on an inverse-follow-the-leader feedback structure with an input distribution network to generate the required transmission zeros. The LPF consumes 35 mA from a single 1.8 V power supply and it has a cut-off frequency of 30 MHz with less than 0.7 dB passband ripple and more than 60 dB stopband attenuation. In addition, a 65 dB dynamic range is achieved.