Stochastic variation of process parameters within a die and technology-limitation-driven variation from die-to-die give rise to unique distribution patterns for manufacturing process parameters. These patterns work as a process signature that is transferred from the device level to the system level through electrical circuits and can be used to make a distinction among the processes. In this work, we propose an in-situ manufacturing process technology distinction method, radio frequency process specific functions (RF-PSFs), that uses process-specific inherent properties of an IC manifested in the transmitted radio frequency signal. Among many desirable testing criteria, RF-PSF addresses the question of fabrication with the intended process technology. This information plays an important role in modern zero-trust architecture and IC clone detection, a counterfeiting method where the IC is manufactured using a different process. An RF transmitter with RF-DAC power amplifier for QPSK modulation has been designed and simulated in 14, 22, and 65 nm processes for five process corners (TT, FF, FS, SF, and SS) in Cadence. The simulated data have been processed in MATLAB. A multilayer perceptron (MLP), trained with the constellation data, provides an average accuracy of${\sim }90\%$for process distinction. Realizing that: 1) a higher order modulation will have even more process information and 2) we can harness the convolutional neural network’s (CNNs) improved capability on pattern recognition, we can feed image-like constellation plots to a CNN to get better and consistent performance. Using the baseband constellations for 64-QAM modulated data as images, we have achieved${\sim }100\%$accuracy with commonly used, pretrained CNN models (ResNet18, ResNet50, and GoogleNet) through transfer learning. The separation among five process corners within a process, termed intraprocess variation, is also analyzed. The effect of baseband sampling rate and ADC resolution, two practical limitations in RF systems, have been explored. An extensive study has been performed on the effect of a key design parameter at the RF circuit level, i.e., W/L or aspect ratio, leading to design insights, proper CNN selection, and some control parameters. This work establishes RF-PSF as a zero-power, zero-area overhead, and in-situ process distinction method.

This article presents a highly linear BiCMOS sample and hold amplifier (SHA) providing 2.8 GS/s intermediate frequency (IF) sampling for a 1 GHz bandwidth input spanning from 1.5 GHz to 2.5 GHz. A single-transistor hold-mode feedthrough cancellation technique is implemented to remove the distortion resulting from the nonlinear parasitic capacitance at the sampling node. The SHA is designed in a mainstream 130 nm BiCMOS technology using SiGe heterojunction bipolar transistors (HBTs) to buffer and sample the wide-band input. Potential inclusion of this BiCMOS SHA in a subsequent high-speed ADC design provides the possibility for a monolithic high performance converter solution. This independent sampling front-end occupies a core chip area of 0.6 mm2. The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers (THA), a high-speed clock driver, and externally adjustable current mirror biases. Measurements of the fabricated SHA show a 10-bit effective resolution across the 1 GHz bandwidth and > 61 dBc spurious free dynamic range (SFDR).