Multiprocessor systems-on-chip (MPSoCs) have become the foundation of critical applications in AI, IoT, and autonomous systems. The Network-on-Chip (NoC) is the communication backbone of MPSoCs, enabling smooth and scalable communication between processing elements. Keeping it secure against evolving threats is imperative. Modern processor vulnerabilities expose MPSoCs to threats like timing side-channel (TSC) and denial-of-service (DoS) attacks, where attackers can infect IP blocks at runtime to target the NoC. This is especially concerning in shared-resource environments, where the lack of strict isolation between components enables wider propagation of such attacks. Routing within isolated secure zones can efficiently deal with such attacks. However, existing secure-zone-based approaches are based on routing tables, which become inefficient and unscalable with increases in NoC sizes, necessitating an adaptive and logic-based approach. Although the scalability offered by the latter increases, it is limited in coverage of complex topologies. This paper presents a logic-based distributed routing strategy using the divide-and-conquer principle (LBDRr). It enhances the topological coverage of traditional LBDR methodologies by dividing irregular topologies into a combination of minimal path sub-topologies. (LBDRr) is used to isolate sensitive data within secure zones, ensuring the system’s integrity against interapplication attacks. Experimental results validate the efficacy of the proposed routing algorithm. Its performance was evaluated by comparison with a state-of-the-art routing table-based approach, demonstrating improved performance, security, and scalability.

The rise of Hardware Trojans (HTs) presents a major threat to the dependability of contemporary electronic systems. Logic testing-based HT detection can identify HTs without a reference-free or golden circuit. In this work, we present a survey of current logic testing-based HT detection that considers Sandia Controllability/ Observability Analysis Program (SCOAP) factors. In order to detect HTs with unique features, the community may use this survey to summarize how SCOAP parameters have been modified over time and are widely utilized as features for machine learning and threshold-based HT detection. We evaluate the state of work to date and outline the main areas for future research in our conclusion.

Nowadays, digital devices like sensors, cell phones, and home servers are deeply embedded in our world to make our daily lives easier. Since we heavily rely on these systems, it is crucial to guarantee their correct functionality and to ensure security and privacy properties. As systems become increasingly complex, it is difficult to maintain security since it necessitates a thorough understanding of all functionalities in hardware and software. Complexity may lead to vulnerabilities that malicious components can exploit. These components can compromise security features provided by the processing cores and the operating system (OS), jeopardizing the overall trustworthiness of the system. In this article, we provide a secure-by-default hardware/OS co-design to build a substrate for trustworthy computing in digital devices. The design is based on a tiled architecture that can integrate untrusted hardware components. Instead of relying on isolation mechanisms of potentially malicious components, isolation is achieved by dedicated and independent hardware components called trusted communication units (TCUs). By keeping the attack surface small and isolating all components by default, malicious hardware and software are restricted in access permissions and, hence, cannot easily break the system’s security. We implemented a TCU-based multiprocessor architecture in a silicon research chip, called Masur23, and ran transfer workloads and selected portions of the microkernel-based OS M3. Our measurements demonstrate the feasibility of such a hardware/OS co-design for trustworthy computing. Compared to the entire chip implementation, security features require minimal latency, area, and power consumption overhead.

Sharing tightly coupled memory in a multiprocessor system-on-chip is a promising approach to improve the programming flexibility as well as to ease the constraints imposed by area and power. However, it poses a challenge in terms of access latency. In this paper, we present a queue based memory management unit which combines the low latency access of shared tightly coupled memory with the flexibility of a traditional memory management unit. Our passive conflict detection approach significantly reduces the critical path compared to previously proposed methods while preserving the flexibility associated with dynamic memory allocation and heterogeneous data widths.

5G is not one problem and one solution, but spans a breadth of applications with largely differing requirements. One solution for all seems therefore inadequate. We therefore present a modular signal processor MPSoC architecture which can be tiled into the size to address the requirement as needed. We name it “Kachel”, the German word for “tile”.

Sharing scratchpad memory improves memory utilization but incurs conflicts. Existing statistical models for throughput estimation of shared memory systems assume mainly online memory arbitration, i.e., the memory access and arbitration logic are integrated into a single path. However, these models are not suited for modeling memory systems deploying off-line arbitration as they do not reflect the additional latency of such arbiters. To cope with this problem, we extend the existing occupancy and Markov models by including appropriate weighing parameters. We show that our extension can reduce the error of the original model by 71 percent over a wide range of parameters.

Current and future applications impose high demands on software-defined radio (SDR) platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous SDR MPSoC with a hexagonal network-on-chip to address these issues. It features four data processing modules and a baseband processing engine for iterative multiple-input multiple-output (MIMO) receiving. Integrated memory controllers enable dynamic data flow mapping and application isolation. In a 4 x 4 MIMO application scenario, the MPSoC achieves a throughput of 232 Mbit/s with a latency of 20 μs while consuming 414 mW. It outperforms state-of-the-art platforms in terms of throughput by a factor of 4.

This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental data-intensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.