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Emmanuelle M. Grafals

dblp:180/3767 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Emerging computing paradigms · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms › memristive computing
dot-product engine
0.212016
Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication · DAC 2016
Hardware accelerators and domain-specific architectures
matrix-vector multiplication
0.212016
Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication · DAC 2016
Hardware accelerators and domain-specific architectures › machine learning accelerator › in-memory computing accelerator
memristive crossbar accelerator
0.212016
Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication · DAC 2016
Emerging computing paradigms
neuromorphic computing
0.212016
Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication · DAC 2016

Methods — techniques the papers use, named apart from their topics

conversion algorithm · 0.2closed-loop pulse tuning · 0.2DAC/ADC · 0.2
YearPublicationVenuePosition
2016 Dot-product engine for neuromorphic computing: programming 1T1M crossbar to accelerate matrix-vector multiplication
abstract
Vector-matrix multiplication dominates the computation time and energy for many workloads, particularly neural network algorithms and linear transforms (e.g, the Discrete Fourier Transform). Utilizing the natural current accumulation feature of memristor crossbar, we developed the Dot-Product Engine (DPE) as a high density, high power efficiency accelerator for approximate matrix-vector multiplication. We firstly invented a conversion algorithm to map arbitrary matrix values appropriately to memristor conductances in a realistic crossbar array, accounting for device physics and circuit issues to reduce computational errors. The accurate device resistance programming in large arrays is enabled by close-loop pulse tuning and access transistors. To validate our approach, we simulated and benchmarked one of the state-of-the-art neural networks for pattern recognition on the DPEs. The result shows no accuracy degradation compared to software approach (99 % pattern recognition accuracy for MNIST data set) with only 4 Bit DAC/ADC requirement, while the DPE can achieve a speed-efficiency product of 1,000× to 10,000× compared to a custom digital ASIC.
Miao Hu 0002, John Paul Strachan, Emmanuelle M. Grafals, Noraica Dávila, Catherine Graves, Sity Lam, Ning Ge 0001, J. Joshua Yang, R. Stanley Williams
DAC4