Hermann Hensel

dblp:180/3813 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Memory systems · 12% Interconnection networks and networks-on-chip · 12%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
database accelerator
0.212016
An MPSoC for energy-efficient database query processing · DAC 2016
Hardware accelerators and domain-specific architectures › query processing
energy-efficient query processing
0.212016
An MPSoC for energy-efficient database query processing · DAC 2016
Memory systems
processing-in-memory
0.112016
An MPSoC for energy-efficient database query processing · DAC 2016

Methods — techniques the papers use, named apart from their topics

runtime task scheduling · 0.2instruction set extension · 0.2dynamic voltage and frequency scaling · 0.2
YearPublicationVenuePosition
2016 An MPSoC for energy-efficient database query processing
abstract
This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental data-intensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.
Sebastian Haas, Oliver Arnold, Benedikt Noethen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann 0002, Stephan Henker, Thomas Hocker, Jörg Schreiter, Holger Eisenreich, Jens-Uwe Schluessler, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen 0014, Hermann Hensel, Sadia Moriam, Emil Matús, Christian Mayr 0001, René Schüffny, Gerhard P. Fettweis
DAC20