This paper presents a survey of the principal architectures and blocks building up a flash memory, describing how these blocks are designed and how their design has changed over the years to satisfy the new specification requests. For example, the continuous supply voltage reduction aimed at portable electronic solutions has forced designers to find innovative design solutions. An overview of the test modes developed for the flash device not only to debug the chip but also to try to improve reliability is given. Ad hoc test modes are useful to deeply increase the analysis capability. Finally, the test methodology for flash memories, a challenge between the test time reduction and better test coverage, is presented.

In the past few years, the complexity of logic functions and architectures inside a flash memory device has grown in order to face the need for more complex system interfaces and to manage the increased amount of stored data. In this paper, an overview of these developments will be given. The paper is divided into sections describing areas where logic circuits play a key role: program/erase algorithms handling and user interface, redundancy management for yield enhancement, error correction codes to enhance reliability, and burst and page mode access control to enhance read bandwidth.