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EDBT 2026 Demo / reviewers in the wild / expert

Paul E. Wood Jr.

dblp:180/6333 · also Paul E. Wood · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1965
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 33% Processor architecture and microarchitecture · 29% Hardware reliability and fault tolerance · 22%

Topics — the 4 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › special-purpose processor
digital differential analyzer		 0.011965
Digital Differential Analyzers with Arbitrary Stored Interconnections · IEEE Trans. Electron. Comput. 1965
Electronic design automation › hardware verification and test
hazard analysis		 0.011964
Hazards in Pulse Sequential Circuits · IEEE Trans. Electron. Comput. 1964
Electronic design automation › hardware verification and test › functional verification
logic verification		 0.011964
Hazards in Pulse Sequential Circuits · IEEE Trans. Electron. Comput. 1964
Integrated circuit design › digital circuit design › threshold logic
threshold logic circuits		 0.011963
A Note On Threshold Device Error Analysis · IEEE Trans. Electron. Comput. 1963

Methods — techniques the papers use, named apart from their topics

performance tradeoff analysis · 0.0hazard analysis · 0.0error analysis · 0.0architectural classification · 0.0
YearPublicationVenuePosition
1965 Digital Differential Analyzers with Arbitrary Stored Interconnections
abstract
A classification scheme for DDA structures is presented. Various structures are examined with respect to speed of operation and the case of providing stored interconnections. A class of DDAs with a staggered parallel structure is presented and discussed. The use of this DDA structure together with ultrasonic delay lines allows arbitrary, stored interconnections and DDA operation at approximately analog computer speed and accuracy. Various trades between equipment cost, speed of operation, and the number of integrator units are considered for DDAs in this class.
Paul E. Wood Jr.
 IEEE Trans. Electron. Comput.1
1964 Hazards in Pulse Sequential Circuits
Paul E. Wood Jr.
 IEEE Trans. Electron. Comput.1
1963 A Note On Threshold Device Error Analysis
Paul E. Wood Jr.
 IEEE Trans. Electron. Comput.1