Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

G. Cooke

dblp:180/6360 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1964
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 60% Electronic design automation · 40%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.011964
Majority Gate Networks · IEEE Trans. Electron. Comput. 1964
Electronic design automation
logic synthesis
0.011964
Majority Gate Networks · IEEE Trans. Electron. Comput. 1964
Integrated circuit design › digital circuit design › threshold logic
majority logic circuits
0.011964
Majority Gate Networks · IEEE Trans. Electron. Comput. 1964
Electronic design automation › logic synthesis › boolean function realization
symmetric function synthesis
0.011964
Majority Gate Networks · IEEE Trans. Electron. Comput. 1964
Integrated circuit design › digital circuit design › threshold logic
threshold logic circuits
0.011964
Majority Gate Networks · IEEE Trans. Electron. Comput. 1964

Methods — techniques the papers use, named apart from their topics

threshold function realization · 0.0array network synthesis · 0.0
YearPublicationVenuePosition
1964 Majority Gate Networks
abstract
This paper presents methods for realizing simple threshold functions of n arguments by networks of k-input majority gates, where k≪n. An optimal network realization of the 5-argument majority function using 3-input majority gates is given, and it is then generalized by steps with realizations for the (2n-l)-argument majority function (where n = 3, 4, ...) using (2n-3)-input majority gates, and then for the (2n-1)-argument majority function using (2k-l)-input majority gates (where k≪n). In a final generalization an array network using (2k-l)-input majority gates introduced for the realization of an (m/n), ``simple,'' threshold function (where m = 1, 2, ...,n). The array network is then applied to the synthesis of arbitrary symmetric functions; in the latter synthesis a realization of ``adjustable logic'' is given where, by simple control of network connections, the same network can be made to compute any symmetric function. The specific networks for ``5 by 3's'' (5-argument majority function realized by a 3-input majority gate), ``7 by 5's'', and ``7 by 3's'' are the best known.
Saul Amarel, G. Cooke, Robert O. Winder
IEEE Trans. Electron. Comput.2