The multiple use of a relatively few types of basic building blocks in digital computers requires that the system designer know the actual performance characteristics of these units in order to produce optimum designs. Worst-case analysis procedures do not yield realistic performance data. The performance-prediction technique discussed in this paper is based on the development of empirical mathematical models which relate the performance variables of interest to the pertinent system parameters. Prediction equations are fitted for the logic elements in a parity-check network for rise, fall, delay, and storage times as a function of the fan-in and fan-out of the logic element and the fan-in and fan-out of the stages which drive it. A statistical analysis of the prediction equations is made to determine the validity of the models. The goodness of fit of these models is presented in graphical form.