The authors describe the capability mechanism of a VLSI-based processor that is free from the problems that had plagued earlier capability-based designs. They examine architecture of a VLSI processor that employs a RISC reduced-instruction-set-computer)-like execution unit and a microcoded coprocessor for storage management and relatively complex capability-related operations. The use of a novel technique for creating small object dynamically in the architecture results in protected procedure call times close to (unprotected) call times in conventional machines. The use of 'flat' name-space for objects results in fast capability translation and zero swapping overhead.>

The synthesis of Boolean functions is a process for converting some specification for circuit behavior into an expression (optimal in some sense) for a Boolean function. It has been conventional to specify this behavior by means of a table of combinations (or truth table) in which for each system of values for the input variables (i.e., input state) there is associated either the value 1 or the value 0 or the symbol d [1]. These are called, respectively, ONE states, ZERO states and DON'T CARE states. This specification then identifies a nonempty class of Boolean functions and the process of Boolean function synthesis is to select from this class of functions one capable of being represented most simply.

High-frequency magnetic film parametrons have been made and observed to exhibit two- or three-state operation for a single bias condition. As a two-stable-state device, the magnetic film parametron can be used as a majority decision element in much the same way as the ferrite core parametron. Another useful logical two-state device is a threshold element, in which the input excitation must reach a minimum level to sustain oscillations. The magnetic film inductor, when suitably clocked, can be used as a gate to permit unilateral flow of information in a system. The gating action, controlled by the bias field, can result from the rectified output of a parametron. Proposed logical designs for a two-element binary adder, a binary shift counter, and a shift register are presented. The possibilities of three-state operation are also explored in the logical design of a seven-element ternary full adder.